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| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2017-09-18 11:32:21 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2017-09-22 09:09:58 +0200 |
| commit | bef52aaccaa8904181e29d3695215ed220dae2f2 (patch) | |
| tree | 313bff38038c8decae6a9c71b06829017a02e564 /arch/arm64 | |
| parent | arm64: dts: ls: Add optee node (diff) | |
| download | linux-bef52aaccaa8904181e29d3695215ed220dae2f2.tar.xz linux-bef52aaccaa8904181e29d3695215ed220dae2f2.zip | |
arm64: dts: ls2088a: add pcie support
The physical memory map address and CCSR registers map address are
different between LS2088A and other LS2080A series SoCs.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index 6aa319dae396..aeaef01d375f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -151,6 +151,7 @@ }; &pcie1 { + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -159,6 +160,7 @@ }; &pcie2 { + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -167,6 +169,7 @@ }; &pcie3 { + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -175,6 +178,7 @@ }; &pcie4 { + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 0x38 0x00000000 0x0 0x00002000>; /* configuration space */ |