diff options
author | Mark Brown <broonie@kernel.org> | 2022-07-04 19:02:55 +0200 |
---|---|---|
committer | Will Deacon <will@kernel.org> | 2022-07-05 12:45:47 +0200 |
commit | 8fcc8285c0e312a6d5ec6060c67eba87d2881419 (patch) | |
tree | 9ea59008a1102f47399a76ad9c185314d2d2bbc1 /arch/arm64 | |
parent | arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generation (diff) | |
download | linux-8fcc8285c0e312a6d5ec6060c67eba87d2881419.tar.xz linux-8fcc8285c0e312a6d5ec6060c67eba87d2881419.zip |
arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generation
Automatically generate defines for ID_AA64ISAR2_EL1, using the definitions
in DDI0487H.a. No functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220704170302.2609529-22-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64')
-rw-r--r-- | arch/arm64/include/asm/sysreg.h | 27 | ||||
-rw-r--r-- | arch/arm64/tools/sysreg | 33 |
2 files changed, 33 insertions, 27 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 7f87690e74b3..cd6820f6e819 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -201,8 +201,6 @@ #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) -#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) - #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) @@ -699,31 +697,6 @@ /* Position the attr at the correct index */ #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) -/* id_aa64isar2 */ -#define ID_AA64ISAR2_EL1_BC_SHIFT 28 -#define ID_AA64ISAR2_EL1_APA3_SHIFT 12 -#define ID_AA64ISAR2_EL1_GPA3_SHIFT 8 -#define ID_AA64ISAR2_EL1_RPRES_SHIFT 4 -#define ID_AA64ISAR2_EL1_WFxT_SHIFT 0 - -/* - * Value 0x1 has been removed from the architecture, and is - * reserved, but has not yet been removed from the ARM ARM - * as of ARM DDI 0487G.b. - */ -#define ID_AA64ISAR2_EL1_WFxT_NI 0x0 -#define ID_AA64ISAR2_EL1_WFxT_IMP 0x2 - -#define ID_AA64ISAR2_EL1_APA3_NI 0x0 -#define ID_AA64ISAR2_EL1_APA3_PAuth 0x1 -#define ID_AA64ISAR2_EL1_APA3_EPAC 0x2 -#define ID_AA64ISAR2_EL1_APA3_PAuth2 0x3 -#define ID_AA64ISAR2_EL1_APA3_FPAC 0x4 -#define ID_AA64ISAR2_EL1_APA3_FPACCOMBINE 0x5 - -#define ID_AA64ISAR2_EL1_GPA3_NI 0x0 -#define ID_AA64ISAR2_EL1_GPA3_IMP 0x1 - /* id_aa64pfr0 */ #define ID_AA64PFR0_CSV3_SHIFT 60 #define ID_AA64PFR0_CSV2_SHIFT 56 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 164221177079..da5e925bf624 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -193,8 +193,41 @@ Enum 3:0 DPB 0b0010 DPB2 EndEnum EndSysreg + +Sysreg ID_AA64ISAR2_EL1 3 0 0 6 2 +Res0 63:28 +Enum 27:24 PAC_frac + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 23:20 BC + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 19:16 MOPS + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 15:12 APA3 + 0b0000 NI + 0b0001 PAuth + 0b0010 EPAC + 0b0011 PAuth2 + 0b0100 FPAC + 0b0101 FPACCOMBINE +EndEnum +Enum 11:8 GPA3 + 0b0000 NI 0b0001 IMP EndEnum +Enum 7:4 RPRES + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 3:0 WFxT + 0b0000 NI + 0b0010 IMP +EndEnum EndSysreg Sysreg SCTLR_EL1 3 0 1 0 0 |