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| author | Marc Zyngier <maz@kernel.org> | 2019-10-04 12:03:09 +0200 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2019-10-20 11:47:07 +0200 |
| commit | 6f16371453476fd094760ea3d6f00144e9ae3057 (patch) | |
| tree | 59ec323837bee0ff834014703e1d7fd894757bd7 /arch/arm64 | |
| parent | KVM: arm64: pmu: Fix cycle counter truncation (diff) | |
| download | linux-6f16371453476fd094760ea3d6f00144e9ae3057.tar.xz linux-6f16371453476fd094760ea3d6f00144e9ae3057.zip | |
arm64: KVM: Handle PMCR_EL0.LC as RES1 on pure AArch64 systems
Of PMCR_EL0.LC, the ARMv8 ARM says:
"In an AArch64 only implementation, this field is RES 1."
So be it.
Fixes: ab9468340d2bc ("arm64: KVM: Add access handler for PMCR register")
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/kvm/sys_regs.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 2071260a275b..46822afc57e0 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -632,6 +632,8 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) */ val = ((pmcr & ~ARMV8_PMU_PMCR_MASK) | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E); + if (!system_supports_32bit_el0()) + val |= ARMV8_PMU_PMCR_LC; __vcpu_sys_reg(vcpu, r->reg) = val; } @@ -682,6 +684,8 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, val = __vcpu_sys_reg(vcpu, PMCR_EL0); val &= ~ARMV8_PMU_PMCR_MASK; val |= p->regval & ARMV8_PMU_PMCR_MASK; + if (!system_supports_32bit_el0()) + val |= ARMV8_PMU_PMCR_LC; __vcpu_sys_reg(vcpu, PMCR_EL0) = val; kvm_pmu_handle_pmcr(vcpu, val); kvm_vcpu_pmu_restore_guest(vcpu); |