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| author | Florian Fainelli <f.fainelli@gmail.com> | 2015-03-09 18:54:32 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2015-03-10 11:24:56 +0100 |
| commit | 1b4bd608763e063ea87e20030e05db005e70177f (patch) | |
| tree | c320f551e7e65b5f2e634e463775430636fb9e4b /arch/arm | |
| parent | ARM: drop experimental status of SMP_ON_UP (diff) | |
| download | linux-1b4bd608763e063ea87e20030e05db005e70177f.tar.xz linux-1b4bd608763e063ea87e20030e05db005e70177f.zip | |
ARM: 8309/1: l2c: enforce use of cache-level property
Make sure that we can read the "cache-level" property from the L2 cache
controller node, and ensure its value is 2.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mm/cache-l2x0.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index c6c7696b8db9..8b933dc43e24 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1648,6 +1648,7 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask) struct device_node *np; struct resource res; u32 cache_id, old_aux; + u32 cache_level = 2; np = of_find_matching_node(NULL, l2x0_ids); if (!np) @@ -1680,6 +1681,12 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask) if (!of_property_read_bool(np, "cache-unified")) pr_err("L2C: device tree omits to specify unified cache\n"); + if (of_property_read_u32(np, "cache-level", &cache_level)) + pr_err("L2C: device tree omits to specify cache-level\n"); + + if (cache_level != 2) + pr_err("L2C: device tree specifies invalid cache level\n"); + /* Read back current (default) hardware configuration */ if (data->save) data->save(l2x0_base); |