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| author | Andre Przywara <andre.przywara@arm.com> | 2020-02-28 14:51:02 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2020-03-26 10:52:10 +0100 |
| commit | 28c05e422305c17ce3db7290d997b2a4f1ebee64 (patch) | |
| tree | c5d00233c1c49edb4ae526f8a36465315a9fe3e8 /arch/arm | |
| parent | Merge tag 'qcom-dts-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git... (diff) | |
| download | linux-28c05e422305c17ce3db7290d997b2a4f1ebee64.tar.xz linux-28c05e422305c17ce3db7290d997b2a4f1ebee64.zip | |
arm: dts: calxeda: Basic DT file fixes
The .dts files for the Calxeda machines are quite old, so carry some
sloppy mistakes that the DT schema checker will complain about.
Fix those issues, they should not have any effect on functionality.
Link: https://lore.kernel.org/r/20200228135106.220620-2-andre.przywara@arm.com
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/ecx-2000.dts | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/highbank.dts | 7 |
2 files changed, 3 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts index 5651ae6dc969..8e0489607704 100644 --- a/arch/arm/boot/dts/ecx-2000.dts +++ b/arch/arm/boot/dts/ecx-2000.dts @@ -13,7 +13,6 @@ compatible = "calxeda,ecx-2000"; #address-cells = <2>; #size-cells = <2>; - clock-ranges; cpus { #address-cells = <1>; @@ -83,8 +82,7 @@ intc: interrupt-controller@fff11000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <1>; + #address-cells = <0>; interrupt-controller; interrupts = <1 9 0xf04>; reg = <0xfff11000 0x1000>, diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index f4e4dca6f7e7..9e34d1bd7994 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -13,7 +13,6 @@ compatible = "calxeda,highbank"; #address-cells = <1>; #size-cells = <1>; - clock-ranges; cpus { #address-cells = <1>; @@ -96,7 +95,7 @@ }; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x00000000 0xff900000>; @@ -128,14 +127,12 @@ intc: interrupt-controller@fff11000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <1>; interrupt-controller; reg = <0xfff11000 0x1000>, <0xfff10100 0x100>; }; - L2: l2-cache { + L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0xfff12000 0x1000>; interrupts = <0 70 4>; |