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| author | Claudiu Manoil <claudiu.manoil@freescale.com> | 2015-07-28 16:43:56 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2015-08-11 17:15:22 +0200 |
| commit | 055223d4d22da918c3d4dae9122736dfd23ec4a4 (patch) | |
| tree | 257fccfda985825c84f18dd9a2956b62c5bfe136 /arch/arm | |
| parent | ARM: dts: ls1021a: Add the eTSEC controller nodes (diff) | |
| download | linux-055223d4d22da918c3d4dae9122736dfd23ec4a4.tar.xz linux-055223d4d22da918c3d4dae9122736dfd23ec4a4.zip | |
ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR
This enables the available eTSEC ethernet ports for the
ls1021aqds and ls1021atwr boards.
For the QDS, SGMII connections (via riser cards) are assumed
for the eTSEC0 and eTSEC1 ports as default configuration.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/ls1021a-qds.dts | 20 | ||||
| -rw-r--r-- | arch/arm/boot/dts/ls1021a-twr.dts | 20 |
2 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts index 4e64f38c35c6..0521e6864cb7 100644 --- a/arch/arm/boot/dts/ls1021a-qds.dts +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -124,6 +124,26 @@ }; }; +&enet0 { + tbi-handle = <&tbi0>; + phy-handle = <&sgmii_phy1c>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet1 { + tbi-handle = <&tbi0>; + phy-handle = <&sgmii_phy1d>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet2 { + phy-handle = <&rgmii_phy3>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + &i2c0 { status = "okay"; diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts index db41e4f63f7e..e008f9367510 100644 --- a/arch/arm/boot/dts/ls1021a-twr.dts +++ b/arch/arm/boot/dts/ls1021a-twr.dts @@ -122,6 +122,26 @@ }; }; +&enet0 { + tbi-handle = <&tbi1>; + phy-handle = <&sgmii_phy2>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet1 { + tbi-handle = <&tbi1>; + phy-handle = <&sgmii_phy0>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet2 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + &i2c0 { status = "okay"; }; |