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| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-10-20 08:47:40 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-11-22 15:32:08 +0100 |
| commit | 95f4b4f44414beac97b4221e2c219a1d0b719d1b (patch) | |
| tree | 718a71a9af7bdbe8bf789dd66f95ff4aeb7fcc25 /arch/arm | |
| parent | ARM: dts: sun6i: Add A31 LCD0 RGB888 pins (diff) | |
| download | linux-95f4b4f44414beac97b4221e2c219a1d0b719d1b.tar.xz linux-95f4b4f44414beac97b4221e2c219a1d0b719d1b.zip | |
ARM: gr8: Add the UART3
The GR8 has access to the UART3 controller, which was missing in the
DTSI. Add it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/sun5i-gr8.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi index ca54e03ef366..d7cf6be2549c 100644 --- a/arch/arm/boot/dts/sun5i-gr8.dtsi +++ b/arch/arm/boot/dts/sun5i-gr8.dtsi @@ -978,6 +978,16 @@ status = "disabled"; }; + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 19>; + status = "disabled"; + }; + i2c0: i2c@01c2ac00 { compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; |