diff options
| author | Jagan Teki <jagannadh.teki@gmail.com> | 2017-10-16 19:13:07 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2017-10-17 21:13:16 +0200 |
| commit | c09cd2537097985e9030a25dfe52d98f2fb9a1ad (patch) | |
| tree | 216d9e1b8e09bb4fc7a81691076c7b91f86d3565 /arch/arm | |
| parent | ARM: dts: rockchip: Add regulators for rk3288-vyasa (diff) | |
| download | linux-c09cd2537097985e9030a25dfe52d98f2fb9a1ad.tar.xz linux-c09cd2537097985e9030a25dfe52d98f2fb9a1ad.zip | |
ARM: dts: rockchip: Add gmac support for rk3288-vyasa board
Add the external clock-reference, enable the gmac node
and define the phy-related pin settings.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/rk3288-vyasa.dts | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts index 738796add05e..3672a0dcb802 100644 --- a/arch/arm/boot/dts/rk3288-vyasa.dts +++ b/arch/arm/boot/dts/rk3288-vyasa.dts @@ -104,12 +104,35 @@ regulator-boot-on; vin-supply = <&dc12_vbat>; }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; }; &cpu0 { cpu0-supply = <&vdd_cpu>; }; +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + &gpu { mali-supply = <&vdd_gpu>; status = "okay"; @@ -361,6 +384,24 @@ }; &pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + pmic { pmic_int: pmic-int { rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; |