diff options
author | Syed Mohammed, Khasim <x0khasim@ti.com> | 2007-06-22 06:48:07 +0200 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2008-02-08 19:38:00 +0100 |
commit | 471b3aa70c2ba00e1a8c8399f848cbc04fd0beae (patch) | |
tree | 3601fc47ee59160ad209d8f08532304009124676 /arch/arm | |
parent | ARM: OMAP: Add DMA support for chaining and 3430 (diff) | |
download | linux-471b3aa70c2ba00e1a8c8399f848cbc04fd0beae.tar.xz linux-471b3aa70c2ba00e1a8c8399f848cbc04fd0beae.zip |
ARM: OMAP: Pre-3430 clean-up for dmtimer.c
Cleanup DM timer list for OMAP2 and OMAP1 to allow
adding support for 3430.
Signed-off-by: Syed Mohammed Khasim <x0khasim@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/plat-omap/dmtimer.c | 65 |
1 files changed, 41 insertions, 24 deletions
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 3856f5aedfc1..0b5689edf2f2 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -48,7 +48,7 @@ #define OMAP_TIMER_COUNTER_REG 0x28 #define OMAP_TIMER_LOAD_REG 0x2c #define OMAP_TIMER_TRIGGER_REG 0x30 -#define OMAP_TIMER_WRITE_PEND_REG 0x34 +#define OMAP_TIMER_WRITE_PEND_REG 0x34 #define OMAP_TIMER_MATCH_REG 0x38 #define OMAP_TIMER_CAPTURE_REG 0x3c #define OMAP_TIMER_IF_CTRL_REG 0x40 @@ -82,8 +82,11 @@ struct omap_dm_timer { #define omap_dm_clk_enable(x) #define omap_dm_clk_disable(x) +#define omap2_dm_timers NULL +#define omap2_dm_source_names NULL +#define omap2_dm_source_clocks NULL -static struct omap_dm_timer dm_timers[] = { +static struct omap_dm_timer omap1_dm_timers[] = { { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 }, { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 }, @@ -94,12 +97,15 @@ static struct omap_dm_timer dm_timers[] = { { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 }, }; +static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers); + #elif defined(CONFIG_ARCH_OMAP2) -#define omap_dm_clk_enable(x) clk_enable(x) -#define omap_dm_clk_disable(x) clk_disable(x) +#define omap_dm_clk_enable(x) clk_enable(x) +#define omap_dm_clk_disable(x) clk_disable(x) +#define omap1_dm_timers NULL -static struct omap_dm_timer dm_timers[] = { +static struct omap_dm_timer omap2_dm_timers[] = { { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 }, { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 }, @@ -114,13 +120,15 @@ static struct omap_dm_timer dm_timers[] = { { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 }, }; -static const char *dm_source_names[] = { +static const char *omap2_dm_source_names[] __initdata = { "sys_ck", "func_32k_ck", - "alt_ck" + "alt_ck", + NULL }; -static struct clk *dm_source_clocks[3]; +static struct clk **omap2_dm_source_clocks[3]; +static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers); #else @@ -128,7 +136,10 @@ static struct clk *dm_source_clocks[3]; #endif -static const int dm_timer_count = ARRAY_SIZE(dm_timers); +static struct omap_dm_timer *dm_timers; +static char **dm_source_names; +static struct clk **dm_source_clocks; + static spinlock_t dm_timer_lock; static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg) @@ -486,7 +497,7 @@ int omap_dm_timers_active(void) return 0; } -int omap_dm_timer_init(void) +int __init omap_dm_timer_init(void) { struct omap_dm_timer *timer; int i; @@ -495,27 +506,33 @@ int omap_dm_timer_init(void) return -ENODEV; spin_lock_init(&dm_timer_lock); -#ifdef CONFIG_ARCH_OMAP2 - for (i = 0; i < ARRAY_SIZE(dm_source_names); i++) { - dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]); - BUG_ON(dm_source_clocks[i] == NULL); + + if (cpu_class_is_omap1()) + dm_timers = omap1_dm_timers; + else if (cpu_is_omap24xx()) { + dm_timers = omap2_dm_timers; + dm_source_names = (char **)omap2_dm_source_names; + dm_source_clocks = (struct clk **)omap2_dm_source_clocks; } -#endif + + if (cpu_class_is_omap2()) + for (i = 0; dm_source_names[i] != NULL; i++) + dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]); + if (cpu_is_omap243x()) dm_timers[0].phys_base = 0x49018000; for (i = 0; i < dm_timer_count; i++) { -#ifdef CONFIG_ARCH_OMAP2 - char clk_name[16]; -#endif - timer = &dm_timers[i]; - timer->io_base = (void __iomem *) io_p2v(timer->phys_base); + timer->io_base = (void __iomem *)io_p2v(timer->phys_base); #ifdef CONFIG_ARCH_OMAP2 - sprintf(clk_name, "gpt%d_ick", i + 1); - timer->iclk = clk_get(NULL, clk_name); - sprintf(clk_name, "gpt%d_fck", i + 1); - timer->fclk = clk_get(NULL, clk_name); + if (cpu_class_is_omap2()) { + char clk_name[16]; + sprintf(clk_name, "gpt%d_ick", i + 1); + timer->iclk = clk_get(NULL, clk_name); + sprintf(clk_name, "gpt%d_fck", i + 1); + timer->fclk = clk_get(NULL, clk_name); + } #endif } |