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authorAlexandre Ghiti <alexghiti@rivosinc.com>2023-12-12 22:34:56 +0100
committerDennis Zhou <dennis@kernel.org>2023-12-14 09:23:17 +0100
commit7a92fc8b4d20680e4c20289a670d8fca2d1f2c1b (patch)
treef02aada180e46f0f74910d88d85b96c0f181061e /arch/arm
parentLinux 6.7-rc4 (diff)
downloadlinux-7a92fc8b4d20680e4c20289a670d8fca2d1f2c1b.tar.xz
linux-7a92fc8b4d20680e4c20289a670d8fca2d1f2c1b.zip
mm: Introduce flush_cache_vmap_early()
The pcpu setup when using the page allocator sets up a new vmalloc mapping very early in the boot process, so early that it cannot use the flush_cache_vmap() function which may depend on structures not yet initialized (for example in riscv, we currently send an IPI to flush other cpus TLB). But on some architectures, we must call flush_cache_vmap(): for example, in riscv, some uarchs can cache invalid TLB entries so we need to flush the new established mapping to avoid taking an exception. So fix this by introducing a new function flush_cache_vmap_early() which is called right after setting the new page table entry and before accessing this new mapping. This new function implements a local flush tlb on riscv and is no-op for other architectures (same as today). Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Dennis Zhou <dennis@kernel.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/include/asm/cacheflush.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index f6181f69577f..1075534b0a2e 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -340,6 +340,8 @@ static inline void flush_cache_vmap(unsigned long start, unsigned long end)
dsb(ishst);
}
+#define flush_cache_vmap_early(start, end) do { } while (0)
+
static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
{
if (!cache_is_vipt_nonaliasing())