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| author | Paul Walmsley <paul@pwsan.com> | 2009-07-25 03:44:01 +0200 |
|---|---|---|
| committer | paul <paul@twilight.(none)> | 2009-07-25 03:44:01 +0200 |
| commit | 75f251e3d0803b028f3474fdc75be0994c377ab5 (patch) | |
| tree | fde30e84a66fad4852d6c18131bc260afecc5b7b /arch/arm | |
| parent | OMAP3: Setup MUX settings for SDRC CKE signals (diff) | |
| download | linux-75f251e3d0803b028f3474fdc75be0994c377ab5.tar.xz linux-75f251e3d0803b028f3474fdc75be0994c377ab5.zip | |
OMAP2/3 SDRC: don't set SDRC_POWER.PWDENA on boot
Stop setting SDRC_POWER.PWDENA on boot. There is a nasty erratum
(34xx erratum 1.150) that can cause memory corruption if PWDENA is
enabled.
Based originally on a patch from Samu P. Onkalo <samu.p.onkalo@nokia.com>.
Tested on BeagleBoard rev C2.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Samu P. Onkalo <samu.p.onkalo@nokia.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-omap2/sdrc.c | 5 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/sram34xx.S | 2 |
2 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c index 2e9e38db30e9..9e3bd4fa7810 100644 --- a/arch/arm/mach-omap2/sdrc.c +++ b/arch/arm/mach-omap2/sdrc.c @@ -125,8 +125,11 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, sdrc_init_params_cs1 = sdrc_cs1; /* XXX Enable SRFRONIDLEREQ here also? */ + /* + * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA + * can cause random memory corruption + */ l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | - (1 << SDRC_POWER_PWDENA_SHIFT) | (1 << SDRC_POWER_PAGEPOLICY_SHIFT); sdrc_write_reg(l, SDRC_POWER); } diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 3aef7448b2a5..9c2d0465a83c 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -58,7 +58,6 @@ /* SDRC_POWER bit settings */ #define SRFRONIDLEREQ_MASK 0x40 -#define PWDENA_MASK 0x4 /* CM_IDLEST1_CORE bit settings */ #define ST_SDRC_MASK 0x2 @@ -160,7 +159,6 @@ sdram_in_selfrefresh: ldr r12, [r11] @ read the contents of SDRC_POWER mov r9, r12 @ keep a copy of SDRC_POWER bits orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle - bic r12, r12, #PWDENA_MASK @ clear PWDENA str r12, [r11] @ write back to SDRC_POWER register ldr r12, [r11] @ posted-write barrier for SDRC idle_sdrc: |