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| author | Michal Marek <mmarek@suse.cz> | 2010-10-12 15:09:06 +0200 |
|---|---|---|
| committer | Michal Marek <mmarek@suse.cz> | 2010-10-12 15:09:06 +0200 |
| commit | 239060b93bb30a4ad55f1ecaa512464a035cc5ba (patch) | |
| tree | 77f79810e57d4fc24356eca0cd6db463e8994128 /arch/blackfin/Kconfig | |
| parent | kconfig: Use PATH_MAX instead of 128 for path buffer sizes. (diff) | |
| parent | kbuild: fix oldnoconfig to do the right thing (diff) | |
| download | linux-239060b93bb30a4ad55f1ecaa512464a035cc5ba.tar.xz linux-239060b93bb30a4ad55f1ecaa512464a035cc5ba.zip | |
Merge branch 'kbuild/rc-fixes' into kbuild/kconfig
We need to revert the temporary hack in 71ebc01, hence the merge.
Diffstat (limited to 'arch/blackfin/Kconfig')
| -rw-r--r-- | arch/blackfin/Kconfig | 23 |
1 files changed, 15 insertions, 8 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 7051c4ce9b93..45f51869ef07 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -18,6 +18,8 @@ config BLACKFIN def_bool y select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK + select HAVE_DYNAMIC_FTRACE + select HAVE_FTRACE_MCOUNT_RECORD select HAVE_FUNCTION_GRAPH_TRACER select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_TRACE_MCOUNT_TEST @@ -25,6 +27,7 @@ config BLACKFIN select HAVE_KERNEL_GZIP if RAMKERNEL select HAVE_KERNEL_BZIP2 if RAMKERNEL select HAVE_KERNEL_LZMA if RAMKERNEL + select HAVE_KERNEL_LZO if RAMKERNEL select HAVE_OPROFILE select ARCH_WANT_OPTIONAL_GPIOLIB @@ -321,11 +324,6 @@ config BF53x depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) default y -config MEM_GENERIC_BOARD - bool - depends on GENERIC_BOARD - default y - config MEM_MT48LC64M4A2FB_7E bool depends on (BFIN533_STAMP) @@ -607,9 +605,6 @@ comment "Kernel Timer/Scheduler" source kernel/Kconfig.hz -config GENERIC_TIME - def_bool y - config GENERIC_CLOCKEVENTS bool "Generic clock events" default y @@ -846,6 +841,18 @@ config CPLB_SWITCH_TAB_L1 If enabled, the CPLB Switch Tables are linked into L1 data memory. (less latency) +config CACHE_FLUSH_L1 + bool "Locate cache flush funcs in L1 Inst Memory" + default y + help + If enabled, the Blackfin cache flushing functions are linked + into L1 instruction memory. + + Note that this might be required to address anomalies, but + these functions are pretty small, so it shouldn't be too bad. + If you are using a processor affected by an anomaly, the build + system will double check for you and prevent it. + config APP_STACK_L1 bool "Support locating application stack in L1 Scratch Memory" default y |