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| author | Sonic Zhang <sonic.zhang@analog.com> | 2009-06-10 10:57:08 +0200 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-06-13 13:20:07 +0200 |
| commit | 47e9dedb720364e0adff0e99960fa294c6161f71 (patch) | |
| tree | fa5bcb532023a89fa11995e5ceca5ed5dfeabbba /arch/blackfin/include/asm/cache.h | |
| parent | Blackfin: include the cpu compiled version in /proc/cpuinfo (diff) | |
| download | linux-47e9dedb720364e0adff0e99960fa294c6161f71.tar.xz linux-47e9dedb720364e0adff0e99960fa294c6161f71.zip | |
Blackfin: add blackfin_invalidate_entire_icache for SMP systems
The KGDB code uses this when switching processors to make sure the icache
is in a valid state.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/include/asm/cache.h')
| -rw-r--r-- | arch/blackfin/include/asm/cache.h | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h index 86637814cf25..2ef669ed9222 100644 --- a/arch/blackfin/include/asm/cache.h +++ b/arch/blackfin/include/asm/cache.h @@ -34,9 +34,13 @@ #define L1_CACHE_SHIFT_MAX 5 #if defined(CONFIG_SMP) && \ - !defined(CONFIG_BFIN_CACHE_COHERENT) && \ - defined(CONFIG_BFIN_DCACHE) -#define __ARCH_SYNC_CORE_DCACHE + !defined(CONFIG_BFIN_CACHE_COHERENT) +# if defined(CONFIG_BFIN_ICACHE) +# define __ARCH_SYNC_CORE_ICACHE +# endif +# if defined(CONFIG_BFIN_DCACHE) +# define __ARCH_SYNC_CORE_DCACHE +# endif #ifndef __ASSEMBLY__ asmlinkage void __raw_smp_mark_barrier_asm(void); asmlinkage void __raw_smp_check_barrier_asm(void); @@ -51,6 +55,7 @@ static inline void smp_check_barrier(void) } void resync_core_dcache(void); +void resync_core_icache(void); #endif #endif |