diff options
| author | Graf Yang <graf.yang@analog.com> | 2008-11-18 10:48:22 +0100 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2008-11-18 10:48:22 +0100 |
| commit | b8a989893cbdeb6c97a7b5af5f38fb0e480235f9 (patch) | |
| tree | 658cf6df93dac687f0d6b94111d0f53b3dd0177c /arch/blackfin/include/asm/cplb.h | |
| parent | Blackfin arch: SMP supporting patchset: Blackfin header files and machine com... (diff) | |
| download | linux-b8a989893cbdeb6c97a7b5af5f38fb0e480235f9.tar.xz linux-b8a989893cbdeb6c97a7b5af5f38fb0e480235f9.zip | |
Blackfin arch: SMP supporting patchset: Blackfin CPLB related code
Blackfin dual core BF561 processor can support SMP like features.
https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like
In this patch, we provide SMP extend to Blackfin CPLB related code
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/include/asm/cplb.h')
| -rw-r--r-- | arch/blackfin/include/asm/cplb.h | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index 9e8b4035fcec..5f7545d06200 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h @@ -30,7 +30,6 @@ #ifndef _CPLB_H #define _CPLB_H -#include <asm/blackfin.h> #include <mach/anomaly.h> #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) @@ -55,13 +54,24 @@ #endif #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) + +#ifdef CONFIG_SMP +#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) +#define L2_IMEMORY (CPLB_COMMON | CPLB_LOCK) +#define L2_DMEMORY (CPLB_COMMON | CPLB_LOCK) + +#else #ifdef CONFIG_BFIN_L2_CACHEABLE #define L2_IMEMORY (SDRAM_IGENERIC) #define L2_DMEMORY (SDRAM_DGENERIC) #else #define L2_IMEMORY (CPLB_COMMON) #define L2_DMEMORY (CPLB_COMMON) -#endif +#endif /* CONFIG_BFIN_L2_CACHEABLE */ + +#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) +#endif /* CONFIG_SMP */ + #define SDRAM_DNON_CHBL (CPLB_COMMON) #define SDRAM_EBIU (CPLB_COMMON) #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) @@ -71,14 +81,7 @@ #define SIZE_1M 0x00100000 /* 1M */ #define SIZE_4M 0x00400000 /* 4M */ -#ifdef CONFIG_MPU #define MAX_CPLBS 16 -#else -#define MAX_CPLBS (16 * 2) -#endif - -#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ - ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) #define CPLB_ENABLE_ICACHE_P 0 #define CPLB_ENABLE_DCACHE_P 1 |