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| author | Ingo Molnar <mingo@elte.hu> | 2009-08-23 11:18:47 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-08-23 11:18:47 +0200 |
| commit | 8a517c514d5893602cf85c1b4c47afbbc04d2198 (patch) | |
| tree | e7c40f68ef97bb2bdb4c366c0b45437bc049feb1 /arch/blackfin/include/asm/traps.h | |
| parent | x86, cpu: cpu/proc.c display cache alignment and address sizes for 32 bit (diff) | |
| parent | Linux 2.6.31-rc7 (diff) | |
| download | linux-8a517c514d5893602cf85c1b4c47afbbc04d2198.tar.xz linux-8a517c514d5893602cf85c1b4c47afbbc04d2198.zip | |
Merge commit 'v2.6.31-rc7' into x86/cpu
Diffstat (limited to 'arch/blackfin/include/asm/traps.h')
| -rw-r--r-- | arch/blackfin/include/asm/traps.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h index 34f7295fb070..3cdc454cde23 100644 --- a/arch/blackfin/include/asm/traps.h +++ b/arch/blackfin/include/asm/traps.h @@ -111,9 +111,7 @@ level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" #define EXC_0x2A(level) \ "Instruction fetch misaligned address violation\n" \ - level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \ - level " exception, the return address provided in RETX is the destination address which is\n" \ - level " misaligned, rather than the address of the offending instruction.\n" + level " - Attempted misaligned instruction cache fetch.\n" #define EXC_0x2B(level) \ "CPLB protection violation\n" \ level " - Illegal instruction fetch access (memory protection violation).\n" |