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| author | Sonic Zhang <sonic.zhang@analog.com> | 2008-10-09 08:11:57 +0200 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2008-10-09 08:11:57 +0200 |
| commit | f099f39acf7575eff3dee3c562cec4e592876c33 (patch) | |
| tree | 57beb28f62712f061789626ad15eabbe31cc5286 /arch/blackfin/include | |
| parent | Blackfin arch: flags of UART3 mem resource is missing (diff) | |
| download | linux-f099f39acf7575eff3dee3c562cec4e592876c33.tar.xz linux-f099f39acf7575eff3dee3c562cec4e592876c33.zip | |
Blackfin arch: Make L2 SRAM cacheable
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/include')
| -rw-r--r-- | arch/blackfin/include/asm/cplb.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index 05d6f05fb748..9e8b4035fcec 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h @@ -55,7 +55,13 @@ #endif #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) -#define L2_MEMORY (CPLB_COMMON) +#ifdef CONFIG_BFIN_L2_CACHEABLE +#define L2_IMEMORY (SDRAM_IGENERIC) +#define L2_DMEMORY (SDRAM_DGENERIC) +#else +#define L2_IMEMORY (CPLB_COMMON) +#define L2_DMEMORY (CPLB_COMMON) +#endif #define SDRAM_DNON_CHBL (CPLB_COMMON) #define SDRAM_EBIU (CPLB_COMMON) #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) |