diff options
| author | Barry Song <barry.song@analog.com> | 2009-12-02 03:50:43 +0100 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-12-15 06:15:54 +0100 |
| commit | e187837b6f23c99c219ffc1d42aa18567f6e299d (patch) | |
| tree | ebf6dad4112689aca936221027115328fdf4456d /arch/blackfin/kernel/cplb-mpu | |
| parent | Blackfin: drop 4KB reserve at end of memory (diff) | |
| download | linux-e187837b6f23c99c219ffc1d42aa18567f6e299d.tar.xz linux-e187837b6f23c99c219ffc1d42aa18567f6e299d.zip | |
Blackfin: MPU: support XIP in async flash memory
The NOMPU code already supported executing in the async banks, so this
brings the MPU code in line.
Signed-off-by: Barry Song <barry.song@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/kernel/cplb-mpu')
| -rw-r--r-- | arch/blackfin/kernel/cplb-mpu/cplbmgr.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index 69e0e530d70f..930c01c06813 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c @@ -113,11 +113,11 @@ static noinline int dcplb_miss(unsigned int cpu) addr = L2_START; d_data = L2_DMEMORY; } else if (addr >= physical_mem_end) { - if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE - && (status & FAULT_USERSUPV)) { - addr &= ~0x3fffff; + if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) { + addr &= ~(4 * 1024 * 1024 - 1); d_data &= ~PAGE_SIZE_4KB; d_data |= PAGE_SIZE_4MB; + d_data |= CPLB_USER_RD | CPLB_USER_WR; } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) { addr &= ~(1 * 1024 * 1024 - 1); @@ -203,7 +203,12 @@ static noinline int icplb_miss(unsigned int cpu) addr = L2_START; i_data = L2_IMEMORY; } else if (addr >= physical_mem_end) { - if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH + if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) { + addr &= ~(4 * 1024 * 1024 - 1); + i_data &= ~PAGE_SIZE_4KB; + i_data |= PAGE_SIZE_4MB; + i_data |= CPLB_USER_RD; + } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH && (status & FAULT_USERSUPV)) { addr &= ~(1 * 1024 * 1024 - 1); i_data &= ~PAGE_SIZE_4KB; |