diff options
| author | Len Brown <len.brown@intel.com> | 2009-09-19 06:11:26 +0200 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2009-09-19 06:11:26 +0200 |
| commit | c602c65b2f81d14456771d1e3f15d1381f4b7efa (patch) | |
| tree | f1f833c8dd6c1519eeb101be32f7fe54a9605af5 /arch/blackfin/kernel/cplb-nompu/cplbinit.c | |
| parent | SFI: remove unneeded includes (diff) | |
| parent | Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/k... (diff) | |
| download | linux-c602c65b2f81d14456771d1e3f15d1381f4b7efa.tar.xz linux-c602c65b2f81d14456771d1e3f15d1381f4b7efa.zip | |
Merge branch 'linus' into sfi-release
Conflicts:
arch/x86/kernel/setup.c
drivers/acpi/power.c
init/main.c
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch/blackfin/kernel/cplb-nompu/cplbinit.c')
| -rw-r--r-- | arch/blackfin/kernel/cplb-nompu/cplbinit.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index 685f160a5a36..5d8ad503f82a 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -36,7 +36,7 @@ int first_switched_icplb PDT_ATTR; int first_switched_dcplb PDT_ATTR; struct cplb_boundary dcplb_bounds[9] PDT_ATTR; -struct cplb_boundary icplb_bounds[7] PDT_ATTR; +struct cplb_boundary icplb_bounds[9] PDT_ATTR; int icplb_nr_bounds PDT_ATTR; int dcplb_nr_bounds PDT_ATTR; @@ -167,14 +167,21 @@ void __init generate_cplb_tables_all(void) icplb_bounds[i_i++].data = (reserved_mem_icache_on ? SDRAM_IGENERIC : SDRAM_INON_CHBL); } + /* Addressing hole up to the async bank. */ + icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE; + icplb_bounds[i_i++].data = 0; + /* ASYNC banks. */ + icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE; + icplb_bounds[i_i++].data = SDRAM_EBIU; /* Addressing hole up to BootROM. */ icplb_bounds[i_i].eaddr = BOOT_ROM_START; icplb_bounds[i_i++].data = 0; /* BootROM -- largest one should be less than 1 meg. */ icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024); icplb_bounds[i_i++].data = SDRAM_IGENERIC; + if (L2_LENGTH) { - /* Addressing hole up to L2 SRAM, including the async bank. */ + /* Addressing hole up to L2 SRAM. */ icplb_bounds[i_i].eaddr = L2_START; icplb_bounds[i_i++].data = 0; /* L2 SRAM. */ |