diff options
| author | Mike Frysinger <vapier.adi@gmail.com> | 2008-11-18 10:48:22 +0100 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2008-11-18 10:48:22 +0100 |
| commit | cb15e57cc7d68e524f709c9a541b4900df80df16 (patch) | |
| tree | 1562f9bc1d2df008ffbb230f315fb2677154d022 /arch/blackfin/kernel/cplb-nompu | |
| parent | Blackfin arch: do not include init sections in the kernel lock down as it get... (diff) | |
| download | linux-cb15e57cc7d68e524f709c9a541b4900df80df16.tar.xz linux-cb15e57cc7d68e524f709c9a541b4900df80df16.zip | |
Blackfin arch: noMMU CPLB lookup tables can be in L1 SRAM
- unify duplicate page_size_table definitions
- make sure it is placed alongside the other cplb switching code
Pointed-out-by: Michael McTernan <mmcternan@airvana.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/kernel/cplb-nompu')
| -rw-r--r-- | arch/blackfin/kernel/cplb-nompu/cplbmgr.S | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.S b/arch/blackfin/kernel/cplb-nompu/cplbmgr.S index 985f3fc793f6..f4ca76c72394 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.S +++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.S @@ -629,15 +629,20 @@ ENTRY(_cplb_mgr) RTS; ENDPROC(_cplb_mgr) +#ifdef CONFIG_CPLB_SWITCH_TAB_L1 +.section .l1.data +#else .data -.align 4; -_page_size_table: +#endif + +ENTRY(_page_size_table) .byte4 0x00000400; /* 1K */ .byte4 0x00001000; /* 4K */ .byte4 0x00100000; /* 1M */ .byte4 0x00400000; /* 4M */ +END(_page_size_table) -.align 4; -_dcplb_preference: +ENTRY(_dcplb_preference) .byte4 0x00000001; /* valid bit */ .byte4 0x00000002; /* lock bit */ +END(_dcplb_preference) |