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| author | Sonic Zhang <sonic.zhang@analog.com> | 2008-04-24 00:13:37 +0200 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2008-04-24 00:13:37 +0200 |
| commit | b85b82d980526d683dc3b39f2ac1f447fa84a105 (patch) | |
| tree | 116646f10fc37668b4136aa040136354442eeb54 /arch/blackfin/kernel/vmlinux.lds.S | |
| parent | [Blackfin] arch: Add a little bit more runtime info for MPU (diff) | |
| download | linux-b85b82d980526d683dc3b39f2ac1f447fa84a105.tar.xz linux-b85b82d980526d683dc3b39f2ac1f447fa84a105.zip | |
[Blackfin] arch: fix bug - Section data_l1_cacheline_aligned should be defined in link script of kernel
http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3978
Section data_l1_cacheline_aligned should be defined in
link script of kernel, when L1 data sram bank A is not available.
In bf536 with all data cache is enabled, there is no L1 data sram.
Current link script won't define section data_l1.cacheline_aligned in
this case. But, if user select put cacheline_aligned data into l1 sram
in kernel menuconfig, these data will be dropped and access to these
data will trigger data CPLB exception.
Do panic in l1 relocation code as well.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/kernel/vmlinux.lds.S')
| -rw-r--r-- | arch/blackfin/kernel/vmlinux.lds.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S index 7a1200328aca..288dfdbfb611 100644 --- a/arch/blackfin/kernel/vmlinux.lds.S +++ b/arch/blackfin/kernel/vmlinux.lds.S @@ -83,6 +83,11 @@ SECTIONS . = ALIGN(32); *(.data.cacheline_aligned) +#if !L1_DATA_A_LENGTH + . = ALIGN(32); + *(.data_l1.cacheline_aligned) +#endif + DATA_DATA *(.data.*) CONSTRUCTORS |