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authorIngo Molnar <mingo@kernel.org>2018-04-05 09:20:34 +0200
committerIngo Molnar <mingo@kernel.org>2018-04-05 09:20:34 +0200
commitea2a6af517714c52a1209795a03e863e96b460bb (patch)
tree3bd443bc9b23ceeaf3743eaf2d6d35ec63c620c9 /arch/blackfin/mach-bf527
parentsched/cpufreq/schedutil: Fix error path mutex unlock (diff)
parentMerge branch 'syscalls-next' of git://git.kernel.org/pub/scm/linux/kernel/git... (diff)
downloadlinux-ea2a6af517714c52a1209795a03e863e96b460bb.tar.xz
linux-ea2a6af517714c52a1209795a03e863e96b460bb.zip
Merge branch 'linus' into sched/urgent, to pick up fixes and updates
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf527')
-rw-r--r--arch/blackfin/mach-bf527/Kconfig325
-rw-r--r--arch/blackfin/mach-bf527/Makefile5
-rw-r--r--arch/blackfin/mach-bf527/boards/Kconfig38
-rw-r--r--arch/blackfin/mach-bf527/boards/Makefile11
-rw-r--r--arch/blackfin/mach-bf527/boards/ad7160eval.c868
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c992
-rw-r--r--arch/blackfin/mach-bf527/boards/ezbrd.c891
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c1335
-rw-r--r--arch/blackfin/mach-bf527/boards/tll6527m.c946
-rw-r--r--arch/blackfin/mach-bf527/dma.c98
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h290
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bf527.h237
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf527/include/mach/blackfin.h37
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF522.h1095
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF525.h421
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF527.h178
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF522.h1309
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF525.h678
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF527.h391
-rw-r--r--arch/blackfin/mach-bf527/include/mach/dma.h38
-rw-r--r--arch/blackfin/mach-bf527/include/mach/gpio.h69
-rw-r--r--arch/blackfin/mach-bf527/include/mach/irq.h204
-rw-r--r--arch/blackfin/mach-bf527/include/mach/mem_map.h70
-rw-r--r--arch/blackfin/mach-bf527/include/mach/pll.h1
-rw-r--r--arch/blackfin/mach-bf527/include/mach/portmux.h220
-rw-r--r--arch/blackfin/mach-bf527/ints-priority.c79
27 files changed, 0 insertions, 10840 deletions
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig
deleted file mode 100644
index 6df20f9c7bd4..000000000000
--- a/arch/blackfin/mach-bf527/Kconfig
+++ /dev/null
@@ -1,325 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config BF52x
- def_bool y
- depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
-
-if (BF52x)
-
-source "arch/blackfin/mach-bf527/boards/Kconfig"
-
-menu "BF527 Specific Configuration"
-
-comment "Alternative Multiplexing Scheme"
-
-choice
- prompt "SPORT0"
- default BF527_SPORT0_PORTG
- help
- Select PORT used for SPORT0. See Hardware Reference Manual
-
-config BF527_SPORT0_PORTF
- bool "PORT F"
- help
- PORT F
-
-config BF527_SPORT0_PORTG
- bool "PORT G"
- help
- PORT G
-endchoice
-
-choice
- prompt "SPORT0 TSCLK Location"
- depends on BF527_SPORT0_PORTG
- default BF527_SPORT0_TSCLK_PG10
- help
- Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual
-
-config BF527_SPORT0_TSCLK_PG10
- bool "PORT PG10"
- help
- PORT PG10
-
-config BF527_SPORT0_TSCLK_PG14
- bool "PORT PG14"
- help
- PORT PG14
-endchoice
-
-choice
- prompt "UART1"
- default BF527_UART1_PORTF
- help
- Select PORT used for UART1. See Hardware Reference Manual
-
-config BF527_UART1_PORTF
- bool "PORT F"
- help
- PORT F
-
-config BF527_UART1_PORTG
- bool "PORT G"
- help
- PORT G
-endchoice
-
-choice
- prompt "NAND (NFC) Data"
- default BF527_NAND_D_PORTH
- help
- Select PORT used for NAND Data Bus. See Hardware Reference Manual
-
-config BF527_NAND_D_PORTF
- bool "PORT F"
- help
- PORT F
-
-config BF527_NAND_D_PORTH
- bool "PORT H"
- help
- PORT H
-endchoice
-
-comment "Hysteresis/Schmitt Trigger Control"
-config BFIN_HYSTERESIS_CONTROL
- bool "Enable Hysteresis Control"
- help
- The ADSP-BF52x allows to control input hysteresis for Port F,
- Port G and Port H and other processor signal inputs.
- The Schmitt trigger enables can be set only for pin groups.
- Saying Y will overwrite the default reset or boot loader
- initialization.
-
-menu "PORT F"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTF_0_7
- bool "Enable Hysteresis on PORTF {0...7}"
-config GPIO_HYST_PORTF_8_9
- bool "Enable Hysteresis on PORTF {8, 9}"
-config GPIO_HYST_PORTF_10
- bool "Enable Hysteresis on PORTF 10"
-config GPIO_HYST_PORTF_11
- bool "Enable Hysteresis on PORTF 11"
-config GPIO_HYST_PORTF_12_13
- bool "Enable Hysteresis on PORTF {12, 13}"
-config GPIO_HYST_PORTF_14_15
- bool "Enable Hysteresis on PORTF {14, 15}"
-endmenu
-
-menu "PORT G"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTG_0
- bool "Enable Hysteresis on PORTG 0"
-config GPIO_HYST_PORTG_1_4
- bool "Enable Hysteresis on PORTG {1...4}"
-config GPIO_HYST_PORTG_5_6
- bool "Enable Hysteresis on PORTG {5, 6}"
-config GPIO_HYST_PORTG_7_8
- bool "Enable Hysteresis on PORTG {7, 8}"
-config GPIO_HYST_PORTG_9
- bool "Enable Hysteresis on PORTG 9"
-config GPIO_HYST_PORTG_10
- bool "Enable Hysteresis on PORTG 10"
-config GPIO_HYST_PORTG_11_13
- bool "Enable Hysteresis on PORTG {11...13}"
-config GPIO_HYST_PORTG_14_15
- bool "Enable Hysteresis on PORTG {14, 15}"
-endmenu
-
-menu "PORT H"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTH_0_7
- bool "Enable Hysteresis on PORTH {0...7}"
-config GPIO_HYST_PORTH_8
- bool "Enable Hysteresis on PORTH 8"
-config GPIO_HYST_PORTH_9_15
- bool "Enable Hysteresis on PORTH {9...15}"
-endmenu
-
-menu "None-GPIO"
- depends on BFIN_HYSTERESIS_CONTROL
-config NONEGPIO_HYST_TMR0_FS1_PPICLK
- bool "Enable Hysteresis on {TMR0, PPI_FS1, PPI_CLK}"
-config NONEGPIO_HYST_NMI_RST_BMODE
- bool "Enable Hysteresis on {NMI, RESET, BMODE}"
-config NONEGPIO_HYST_JTAG
- bool "Enable Hysteresis on JTAG"
-endmenu
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA0_ERROR
- int "IRQ_DMA0_ERROR"
- default 7
-config IRQ_DMAR0_BLK
- int "IRQ_DMAR0_BLK"
- default 7
-config IRQ_DMAR1_BLK
- int "IRQ_DMAR1_BLK"
- default 7
-config IRQ_DMAR0_OVR
- int "IRQ_DMAR0_OVR"
- default 7
-config IRQ_DMAR1_OVR
- int "IRQ_DMAR1_OVR"
- default 7
-config IRQ_PPI_ERROR
- int "IRQ_PPI_ERROR"
- default 7
-config IRQ_MAC_ERROR
- int "IRQ_MAC_ERROR"
- default 7
-config IRQ_SPORT0_ERROR
- int "IRQ_SPORT0_ERROR"
- default 7
-config IRQ_SPORT1_ERROR
- int "IRQ_SPORT1_ERROR"
- default 7
-config IRQ_UART0_ERROR
- int "IRQ_UART0_ERROR"
- default 7
-config IRQ_UART1_ERROR
- int "IRQ_UART1_ERROR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_TWI
- int "IRQ_TWI"
- default 10
-config IRQ_SPI
- int "IRQ_SPI"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_OPTSEC
- int "IRQ_OPTSEC"
- default 11
-config IRQ_CNT
- int "IRQ_CNT"
- default 11
-config IRQ_MAC_RX
- int "IRQ_MAC_RX"
- default 11
-config IRQ_PORTH_INTA
- int "IRQ_PORTH_INTA"
- default 11
-config IRQ_MAC_TX
- int "IRQ_MAC_TX/NFC"
- default 11
-config IRQ_PORTH_INTB
- int "IRQ_PORTH_INTB"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 12
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 12
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 12
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 12
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 12
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 12
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 12
-config IRQ_PORTG_INTA
- int "IRQ_PORTG_INTA"
- default 12
-config IRQ_PORTG_INTB
- int "IRQ_PORTG_INTB"
- default 12
-config IRQ_MEM_DMA0
- int "IRQ_MEM_DMA0"
- default 13
-config IRQ_MEM_DMA1
- int "IRQ_MEM_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-config IRQ_PORTF_INTA
- int "IRQ_PORTF_INTA"
- default 13
-config IRQ_PORTF_INTB
- int "IRQ_PORTF_INTB"
- default 13
-config IRQ_SPI_ERROR
- int "IRQ_SPI_ERROR"
- default 7
-config IRQ_NFC_ERROR
- int "IRQ_NFC_ERROR"
- default 7
-config IRQ_HDMA_ERROR
- int "IRQ_HDMA_ERROR"
- default 7
-config IRQ_HDMA
- int "IRQ_HDMA"
- default 7
-config IRQ_USB_EINT
- int "IRQ_USB_EINT"
- default 10
-config IRQ_USB_INT0
- int "IRQ_USB_INT0"
- default 10
-config IRQ_USB_INT1
- int "IRQ_USB_INT1"
- default 10
-config IRQ_USB_INT2
- int "IRQ_USB_INT2"
- default 10
-config IRQ_USB_DMA
- int "IRQ_USB_DMA"
- default 10
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf527/Makefile b/arch/blackfin/mach-bf527/Makefile
deleted file mode 100644
index 4a6cdafab8ce..000000000000
--- a/arch/blackfin/mach-bf527/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf527/Makefile
-#
-
-obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf527/boards/Kconfig b/arch/blackfin/mach-bf527/boards/Kconfig
deleted file mode 100644
index a76f02fae11c..000000000000
--- a/arch/blackfin/mach-bf527/boards/Kconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN527_EZKIT
- help
- Select your board!
-
-config BFIN527_EZKIT
- bool "BF527-EZKIT"
- help
- BF527-EZKIT-LITE board support.
-
-config BFIN527_EZKIT_V2
- bool "BF527-EZKIT-V2"
- help
- BF527-EZKIT-LITE V2.1+ board support.
-
-config BFIN527_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF527"
- help
- CM-BF527 support for EVAL- and DEV-Board.
-
-config BFIN526_EZBRD
- bool "BF526-EZBRD"
- help
- BF526-EZBRD/EZKIT Lite board support.
-
-config BFIN527_AD7160EVAL
- bool "BF527-AD7160-EVAL"
- help
- BF527-AD7160-EVAL board support.
-
-config BFIN527_TLL6527M
- bool "The Learning Labs TLL6527M"
- help
- TLL6527M V1.0 platform support
-
-endchoice
diff --git a/arch/blackfin/mach-bf527/boards/Makefile b/arch/blackfin/mach-bf527/boards/Makefile
deleted file mode 100644
index 6ada1537e20a..000000000000
--- a/arch/blackfin/mach-bf527/boards/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-bf527/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN527_EZKIT_V2) += ezkit.o
-obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o
-obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o
-obj-$(CONFIG_BFIN527_AD7160EVAL) += ad7160eval.o
-obj-$(CONFIG_BFIN527_TLL6527M) += tll6527m.o
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
deleted file mode 100644
index 68f2a8a806ea..000000000000
--- a/arch/blackfin/mach-bf527/boards/ad7160eval.c
+++ /dev/null
@@ -1,868 +0,0 @@
-/*
- * Copyright 2004-20010 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF527-AD7160EVAL";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PG13,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_RA158Z)
-static struct resource bf52x_ra158z_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf52x_ra158z_device = {
- .name = "bfin-ra158z",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf52x_ra158z_resources),
- .resource = bf52x_ra158z_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ad7160eval_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ad7160eval_flash_data = {
- .width = 2,
- .parts = ad7160eval_partitions,
- .nr_parts = ARRAY_SIZE(ad7160eval_partitions),
-};
-
-static struct resource ad7160eval_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ad7160eval_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ad7160eval_flash_data,
- },
- .num_resources = 1,
- .resource = &ad7160eval_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "linux kernel(nand)",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 30000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = GPIO_PH3 + MAX_CTRL_CS,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7160)
-#include <linux/input/ad7160.h>
-static const struct ad7160_platform_data bfin_ad7160_ts_info = {
- .sensor_x_res = 854,
- .sensor_y_res = 480,
- .pressure = 100,
- .filter_coef = 3,
- .coord_pref = AD7160_ORIG_TOP_LEFT,
- .first_touch_window = 5,
- .move_window = 3,
- .event_cabs = AD7160_EMIT_ABS_MT_TRACKING_ID |
- AD7160_EMIT_ABS_MT_PRESSURE |
- AD7160_TRACKING_ID_ASCENDING,
- .finger_act_ctrl = 0x64,
- .haptic_effect1_ctrl = AD7160_HAPTIC_SLOT_A(60) |
- AD7160_HAPTIC_SLOT_A_LVL_HIGH |
- AD7160_HAPTIC_SLOT_B(60) |
- AD7160_HAPTIC_SLOT_B_LVL_LOW,
-
- .haptic_effect2_ctrl = AD7160_HAPTIC_SLOT_A(20) |
- AD7160_HAPTIC_SLOT_A_LVL_HIGH |
- AD7160_HAPTIC_SLOT_B(80) |
- AD7160_HAPTIC_SLOT_B_LVL_LOW |
- AD7160_HAPTIC_SLOT_C(120) |
- AD7160_HAPTIC_SLOT_C_LVL_HIGH |
- AD7160_HAPTIC_SLOT_D(30) |
- AD7160_HAPTIC_SLOT_D_LVL_LOW,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7160)
- {
- I2C_BOARD_INFO("ad7160", 0x33),
- .irq = IRQ_PH1,
- .platform_data = (void *)&bfin_ad7160_ts_info,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static const u16 per_cnt[] = {
- P_CNT_CUD,
- P_CNT_CDG,
- P_CNT_CZM,
- 0
-};
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
- .pm_wakeup = 1,
- .pin_list = per_cnt,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] = {
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_RA158Z)
- &bf52x_ra158z_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ad7160eval_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-};
-
-static int __init ad7160eval_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ad7160eval_init);
-
-static struct platform_device *ad7160eval_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ad7160eval_early_devices,
- ARRAY_SIZE(ad7160eval_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
deleted file mode 100644
index b1004b35db36..000000000000
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ /dev/null
@@ -1,992 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/etherdevice.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM-BF527";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x203C0000,
- .end = 0x203C0000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PF11,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "linux kernel(nand)",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x203FB800,
- .end = 0x203FB800 + 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x203FB804,
- .end = 0x203FB804 + 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PH9, GPIO_PG11 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF14, 1, "gpio-keys: BTN0"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cmbf527_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init cm_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(cmbf527_devices, ARRAY_SIZE(cmbf527_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(cm_init);
-
-static struct platform_device *cmbf527_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cmbf527_early_devices,
- ARRAY_SIZE(cmbf527_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
deleted file mode 100644
index 80bcfd1d023e..000000000000
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ /dev/null
@@ -1,891 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF526-EZBRD";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PG13,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezbrd_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezbrd_flash_data = {
- .width = 2,
- .parts = ezbrd_partitions,
- .nr_parts = ARRAY_SIZE(ezbrd_partitions),
-};
-
-static struct resource ezbrd_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezbrd_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezbrd_flash_data,
- },
- .num_resources = 1,
- .resource = &ezbrd_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x40000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "sst25wf040",
-};
-
-/* SPI flash chip (sst25wf040) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* Export GPIO to gpiolib */
- .gpio_base = -1, /* Dynamic allocation */
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PG0,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PG0,
- .end = GPIO_PG0,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 1,
- .gpio_bl = GPIO_PG12,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezbrd_flash_device,
-#endif
-};
-
-static int __init ezbrd_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ezbrd_init);
-
-static struct platform_device *ezbrd_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezbrd_early_devices,
- ARRAY_SIZE(ezbrd_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
deleted file mode 100644
index 571edfd2ecf3..000000000000
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ /dev/null
@@ -1,1335 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/ad7877.h>
-#include <asm/bfin_sport.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-#ifdef CONFIG_BFIN527_EZKIT_V2
-const char bfin_board_name[] = "ADI BF527-EZKIT V2";
-#else
-const char bfin_board_name[] = "ADI BF527-EZKIT";
-#endif
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x203C0000,
- .end = 0x203C0000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PG13,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_T350MCQB)
-
-static struct resource bf52x_t350mcqb_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf52x_t350mcqb_device = {
- .name = "bfin-t350mcqb",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf52x_t350mcqb_resources),
- .resource = bf52x_t350mcqb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_8_BIT_PPI,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x40000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x203FB800,
- .end = 0x203FB800 + 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x203FB800 + 4,
- .end = 0x203FB800 + 5,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 0, /* Export GPIO to gpiolib */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-
-static const u16 bfin_snd_pin[][7] = {
- {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0, 0},
- {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_TFS, 0},
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836",
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 3,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_0,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 3,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 7,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
-#include <linux/mfd/adp5520.h>
-
- /*
- * ADP5520/5501 LEDs Data
- */
-
-static struct led_info adp5520_leds[] = {
- {
- .name = "adp5520-led1",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms,
- },
-};
-
-static struct adp5520_leds_platform_data adp5520_leds_data = {
- .num_leds = ARRAY_SIZE(adp5520_leds),
- .leds = adp5520_leds,
- .fade_in = ADP5520_FADE_T_600ms,
- .fade_out = ADP5520_FADE_T_600ms,
- .led_on_time = ADP5520_LED_ONT_600ms,
-};
-
- /*
- * ADP5520 Keypad Data
- */
-
-static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = {
- [ADP5520_KEY(3, 3)] = KEY_1,
- [ADP5520_KEY(2, 3)] = KEY_2,
- [ADP5520_KEY(1, 3)] = KEY_3,
- [ADP5520_KEY(0, 3)] = KEY_UP,
- [ADP5520_KEY(3, 2)] = KEY_4,
- [ADP5520_KEY(2, 2)] = KEY_5,
- [ADP5520_KEY(1, 2)] = KEY_6,
- [ADP5520_KEY(0, 2)] = KEY_DOWN,
- [ADP5520_KEY(3, 1)] = KEY_7,
- [ADP5520_KEY(2, 1)] = KEY_8,
- [ADP5520_KEY(1, 1)] = KEY_9,
- [ADP5520_KEY(0, 1)] = KEY_DOT,
- [ADP5520_KEY(3, 0)] = KEY_BACKSPACE,
- [ADP5520_KEY(2, 0)] = KEY_0,
- [ADP5520_KEY(1, 0)] = KEY_HELP,
- [ADP5520_KEY(0, 0)] = KEY_ENTER,
-};
-
-static struct adp5520_keys_platform_data adp5520_keys_data = {
- .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0,
- .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0,
- .keymap = adp5520_keymap,
- .keymapsize = ARRAY_SIZE(adp5520_keymap),
- .repeat = 0,
-};
-
- /*
- * ADP5520/5501 Multifunction Device Init Data
- */
-
-static struct adp5520_platform_data adp5520_pdev_data = {
- .leds = &adp5520_leds_data,
- .keys = &adp5520_keys_data,
-};
-
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
- {
- I2C_BOARD_INFO("ad7879", 0x2C),
- .irq = IRQ_PF8,
- .platform_data = (void *)&bfin_ad7879_ts_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
- {
- I2C_BOARD_INFO("pmic-adp5520", 0x32),
- .irq = IRQ_PF9,
- .platform_data = (void *)&adp5520_pdev_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2f),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1373)
- {
- I2C_BOARD_INFO("adau1373", 0x1A),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static const u16 per_cnt[] = {
- P_CNT_CUD,
- P_CNT_CDG,
- P_CNT_CZM,
- 0
-};
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
- .pm_wakeup = 1,
- .pin_list = per_cnt,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_T350MCQB)
- &bf52x_t350mcqb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
deleted file mode 100644
index ce5488e8226b..000000000000
--- a/arch/blackfin/mach-bf527/boards/tll6527m.c
+++ /dev/null
@@ -1,946 +0,0 @@
-/* File: arch/blackfin/mach-bf527/boards/tll6527m.c
- * Based on: arch/blackfin/mach-bf527/boards/ezkit.c
- * Author: Ashish Gupta
- *
- * Copyright: 2010 - The Learning Labs Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-#define LCD_BACKLIGHT_GPIO 0x40
-/* TLL6527M uses TLL7UIQ35 / ADI LCD EZ Extender. AD7879 AUX GPIO is used for
- * LCD Backlight Enable
- */
-#endif
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "TLL6527M";
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- /*.gpio_vrsel = GPIO_PG13,*/
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 1,
- .gpio_bl = LCD_BACKLIGHT_GPIO,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition tll6527m_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0xA0000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0xD00000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data tll6527m_flash_data = {
- .width = 2,
- .parts = tll6527m_partitions,
- .nr_parts = ARRAY_SIZE(tll6527m_partitions),
-};
-
-static unsigned tll6527m_flash_gpios[] = { GPIO_PG11, GPIO_PH11, GPIO_PH12 };
-
-static struct resource tll6527m_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)tll6527m_flash_gpios,
- .end = ARRAY_SIZE(tll6527m_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device tll6527m_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &tll6527m_flash_data,
- },
- .num_resources = ARRAY_SIZE(tll6527m_flash_resource),
- .resource = tll6527m_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_GPIO_DECODER)
-/* An SN74LVC138A 3:8 decoder chip has been used to generate 7 augmented
- * outputs used as SPI CS lines for all SPI SLAVE devices on TLL6527v1-0.
- * EXP_GPIO_SPISEL_BASE is the base number for the expanded outputs being
- * used as SPI CS lines, this should be > MAX_BLACKFIN_GPIOS
- */
-#include <linux/gpio-decoder.h>
-#define EXP_GPIO_SPISEL_BASE 0x64
-static unsigned gpio_addr_inputs[] = {
- GPIO_PG1, GPIO_PH9, GPIO_PH10
-};
-
-static struct gpio_decoder_platform_data spi_decoded_cs = {
- .base = EXP_GPIO_SPISEL_BASE,
- .input_addrs = gpio_addr_inputs,
- .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs),
- .default_output = 0,
-/* .default_output = (1 << ARRAY_SIZE(gpio_addr_inputs)) - 1 */
-};
-
-static struct platform_device spi_decoded_gpio = {
- .name = "gpio-decoder",
- .id = 0,
- .dev = {
- .platform_data = &spi_decoded_cs,
- },
-};
-
-#else
-#define EXP_GPIO_SPISEL_BASE 0x0
-
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl345_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 2,
- .inactivity_time = 2,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
- .ev_code_act_inactivity = KEY_A, /* EV_KEY */
- .use_int2 = 1,
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3,
- /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1,
- /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* configure AUX as GPIO output*/
- .gpio_base = LCD_BACKLIGHT_GPIO,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
-#include <linux/spi/mcp23s08.h>
-static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = {
- .spi_present_mask = BIT(0),
- .base = 0x30,
-};
-static const struct mcp23s08_platform_data bfin_mcp23s08_usr_gpio_info = {
- .spi_present_mask = BIT(2),
- .base = 0x38,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000,
- /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
- /* Can be connected to TLL6527M GPIO connector */
- /* Either SPI_ADC or M25P80 FLASH can be installed at a time */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
-/*
- * TLL6527M V1.0 does not support SD Card at SPI Clock > 10 MHz due to
- * SPI buffer limitations
- */
- .max_speed_hz = 10000000,
- /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x05 + MAX_CTRL_CS,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PH14,
- .max_speed_hz = 5000000,
- /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 10000000,
- /* TLL6527Mv1-0 supports max spi clock (SCK) speed = 10 MHz */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000,
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
- {
- .modalias = "mcp23s08",
- .platform_data = &bfin_mcp23s08_sys_gpio_info,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
- {
- .modalias = "mcp23s08",
- .platform_data = &bfin_mcp23s08_usr_gpio_info,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = EXP_GPIO_SPISEL_BASE + 8 + MAX_CTRL_CS,
- /* EXP_GPIO_SPISEL_BASE will be > MAX_BLACKFIN_GPIOS */
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
- {
- I2C_BOARD_INFO("ad7879", 0x2C),
- .irq = IRQ_PH14,
- .platform_data = (void *)&bfin_ad7879_ts_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
- {
- I2C_BOARD_INFO("adm1192", 0x2e),
- },
-
- {
- I2C_BOARD_INFO("ltc3576", 0x09),
- },
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PH13,
- .platform_data = (void *)&adxl345_info,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] = {
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *tll6527m_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &tll6527m_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_GPIO_DECODER)
- &spi_decoded_gpio,
-#endif
-};
-
-static int __init tll6527m_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(tll6527m_devices, ARRAY_SIZE(tll6527m_devices));
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(tll6527m_init);
-
-static struct platform_device *tll6527m_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(tll6527m_early_devices,
- ARRAY_SIZE(tll6527m_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags,
- u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c
deleted file mode 100644
index 1fabdefea73a..000000000000
--- a/arch/blackfin/mach-bf527/dma.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * This file contains the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_EMAC_RX:
- ret_irq = IRQ_MAC_RX;
- break;
-
- case CH_EMAC_TX:
- ret_irq = IRQ_MAC_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
deleted file mode 100644
index 2f9cc33deec4..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
- * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support old silicon - sorry */
-#if __SILICON_REVISION__ < 0
-# error will not work on BF526/BF527 silicon version
-#endif
-
-#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-# define ANOMALY_BF526 1
-#else
-# define ANOMALY_BF526 0
-#endif
-#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
-# define ANOMALY_BF527 1
-#else
-# define ANOMALY_BF527 0
-#endif
-
-#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)
-#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
-#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (_ANOMALY_BF527(< 2))
-/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
-#define ANOMALY_05000342 (_ANOMALY_BF527(< 2))
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0xE510
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (_ANOMALY_BF527(< 2))
-/* Security Features Are Not Functional */
-#define ANOMALY_05000348 (_ANOMALY_BF527(< 1))
-/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-#define ANOMALY_05000353 (_ANOMALY_BF526(< 1))
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (_ANOMALY_BF527(< 2))
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (_ANOMALY_BF527(< 2))
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000364 (_ANOMALY_BF527(== 1))
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Incorrect Default CSEL Value in PLL_DIV */
-#define ANOMALY_05000368 (_ANOMALY_BF527(< 2))
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (_ANOMALY_BF527(< 2))
-/* Authentication Fails To Initiate */
-#define ANOMALY_05000376 (_ANOMALY_BF527(< 2))
-/* Data Read From L3 Memory by USB DMA May be Corrupted */
-#define ANOMALY_05000380 (_ANOMALY_BF527(< 2))
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (_ANOMALY_BF527(< 2))
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (_ANOMALY_BF527(< 2))
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (_ANOMALY_BF527(< 2))
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (_ANOMALY_BF527(< 2))
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (_ANOMALY_BF527(< 2))
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (_ANOMALY_BF527(< 2))
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (_ANOMALY_BF527(< 2))
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (_ANOMALY_BF527(< 2))
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (_ANOMALY_BF527(< 2))
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (_ANOMALY_BF527(< 2))
-/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
-#define ANOMALY_05000398 (_ANOMALY_BF527(< 2))
-/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
-#define ANOMALY_05000399 (_ANOMALY_BF527(< 2))
-/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
-#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Incorrect Default Internal Voltage Regulator Setting */
-#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
-/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
-/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* DEB2_URGENT Bit Not Functional */
-#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
-#define ANOMALY_05000417 (_ANOMALY_BF527(< 2))
-/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
-#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
-#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
-#define ANOMALY_05000421 (1)
-/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1))
-/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
-#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Internal Voltage Regulator Not Trimmed */
-#define ANOMALY_05000424 (_ANOMALY_BF527(< 2))
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
-#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (_ANOMALY_BF527(> 1))
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (1)
-/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
-#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (_ANOMALY_BF527(< 1))
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* The WURESET Bit in the SYSCR Register is not Functional */
-#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
-/* USB DMA Short Packet Data Corruption */
-#define ANOMALY_05000450 (1)
-/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
-#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
-#define ANOMALY_05000456 (1)
-/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
-#define ANOMALY_05000457 (1)
-/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* USB Rx DMA Hang */
-#define ANOMALY_05000465 (1)
-/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (1)
-/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
-#define ANOMALY_05000467 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
-#define ANOMALY_05000483 (1)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
-/* The CODEC Zero-Cross Detect Feature is not Functional */
-#define ANOMALY_05000487 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bf527.h b/arch/blackfin/mach-bf527/include/mach/bf527.h
deleted file mode 100644
index 8ff155b34f64..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/bf527.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF527_H__
-#define __MACH_BF527_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-/**************************** Hysteresis Settings ****************************/
-
-#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
-#ifdef CONFIG_GPIO_HYST_PORTF_0_7
-#define HYST_PORTF_0_7 (1 << 0)
-#else
-#define HYST_PORTF_0_7 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_8_9
-#define HYST_PORTF_8_9 (1 << 2)
-#else
-#define HYST_PORTF_8_9 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_10
-#define HYST_PORTF_10 (1 << 4)
-#else
-#define HYST_PORTF_10 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_11
-#define HYST_PORTF_11 (1 << 6)
-#else
-#define HYST_PORTF_11 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_12_13
-#define HYST_PORTF_12_13 (1 << 8)
-#else
-#define HYST_PORTF_12_13 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_14_15
-#define HYST_PORTF_14_15 (1 << 10)
-#else
-#define HYST_PORTF_14_15 (0 << 10)
-#endif
-
-#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
- HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTG_0
-#define HYST_PORTG_0 (1 << 0)
-#else
-#define HYST_PORTG_0 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_1_4
-#define HYST_PORTG_1_4 (1 << 2)
-#else
-#define HYST_PORTG_1_4 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_5_6
-#define HYST_PORTG_5_6 (1 << 4)
-#else
-#define HYST_PORTG_5_6 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_7_8
-#define HYST_PORTG_7_8 (1 << 6)
-#else
-#define HYST_PORTG_7_8 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_9
-#define HYST_PORTG_9 (1 << 8)
-#else
-#define HYST_PORTG_9 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_10
-#define HYST_PORTG_10 (1 << 10)
-#else
-#define HYST_PORTG_10 (0 << 10)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_11_13
-#define HYST_PORTG_11_13 (1 << 12)
-#else
-#define HYST_PORTG_11_13 (0 << 12)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_14_15
-#define HYST_PORTG_14_15 (1 << 14)
-#else
-#define HYST_PORTG_14_15 (0 << 14)
-#endif
-
-#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
- HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
- HYST_PORTG_11_13 | HYST_PORTG_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTH_0_7
-#define HYST_PORTH_0_7 (1 << 0)
-#else
-#define HYST_PORTH_0_7 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTH_8
-#define HYST_PORTH_8 (1 << 2)
-#else
-#define HYST_PORTH_8 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTH_9_15
-#define HYST_PORTH_9_15 (1 << 4)
-#else
-#define HYST_PORTH_9_15 (0 << 4)
-#endif
-
-#define HYST_PORTH_0_15 (HYST_PORTH_0_7 | HYST_PORTH_8 | HYST_PORTH_9_15)
-
-#ifdef CONFIG_NONEGPIO_HYST_TMR0_FS1_PPICLK
-#define HYST_TMR0_FS1_PPICLK (1 << 0)
-#else
-#define HYST_TMR0_FS1_PPICLK (0 << 0)
-#endif
-#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
-#define HYST_NMI_RST_BMODE (1 << 2)
-#else
-#define HYST_NMI_RST_BMODE (0 << 2)
-#endif
-#ifdef CONFIG_NONEGPIO_HYST_JTAG
-#define HYST_JTAG (1 << 4)
-#else
-#define HYST_JTAG (0 << 4)
-#endif
-
-#define HYST_NONEGPIO (HYST_TMR0_FS1_PPICLK | HYST_NMI_RST_BMODE | HYST_JTAG)
-#define HYST_NONEGPIO_MASK (0x3F)
-#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
-
-#ifdef CONFIG_BF527
-#define CPU "BF527"
-#define CPUID 0x27e0
-#endif
-#ifdef CONFIG_BF526
-#define CPU "BF526"
-#define CPUID 0x27e4
-#endif
-#ifdef CONFIG_BF525
-#define CPU "BF525"
-#define CPUID 0x27e0
-#endif
-#ifdef CONFIG_BF524
-#define CPU "BF524"
-#define CPUID 0x27e4
-#endif
-#ifdef CONFIG_BF523
-#define CPU "BF523"
-#define CPUID 0x27e0
-#endif
-#ifdef CONFIG_BF522
-#define CPU "BF522"
-#define CPUID 0x27e4
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF527_H__ */
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
deleted file mode 100644
index 00c603fe8218..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h
deleted file mode 100644
index e1d279274487..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/blackfin.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf527.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#if defined(CONFIG_BF523) || defined(CONFIG_BF522)
-# include "defBF522.h"
-#endif
-#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-# include "defBF525.h"
-#endif
-#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-# include "defBF527.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-# include <asm/cdef_LPBlackfin.h>
-# if defined(CONFIG_BF523) || defined(CONFIG_BF522)
-# include "cdefBF522.h"
-# endif
-# if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-# include "cdefBF525.h"
-# endif
-# if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-# include "cdefBF527.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
deleted file mode 100644
index 2c12e879aa4e..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
+++ /dev/null
@@ -1,1095 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF522_H
-#define _CDEF_BF522_H
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
-
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
-#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
-
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
-#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
-
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-
-
-/* DMA Traffic Control Registers */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-
-/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-/* ==== end from cdefBF534.h ==== */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
-
-#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
-#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
-#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
-#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
-#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-
-/* NFC Registers */
-
-#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-
-#endif /* _CDEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
deleted file mode 100644
index bd045318a250..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF525_H
-#define _CDEF_BF525_H
-
-/* BF525 is BF522 + USB */
-#include "cdefBF522.h"
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endpoint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endpoint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-
-/* USB Endpoint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-
-/* USB Endpoint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-
-/* USB Endpoint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-
-/* USB Endpoint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-
-/* USB Endpoint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-
-/* USB Endpoint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-
-/* USB Endpoint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
-
-#endif /* _CDEF_BF525_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
deleted file mode 100644
index eb22f5866105..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF527_H
-#define _CDEF_BF527_H
-
-/* BF527 is BF525 + EMAC */
-#include "cdefBF525.h"
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
-
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* _CDEF_BF527_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h
deleted file mode 100644
index e007017cf958..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/defBF522.h
+++ /dev/null
@@ -1,1309 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF522_H
-#define _DEF_BF522_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
-/* ************************************************************** */
-
-/* ==== begin from defBF534.h ==== */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014 /* Device ID Register */
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
-#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
-
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-
-/* DMA Traffic Control Registers */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_REGBASE 0xFFC01400
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-
-/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
-
-#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-#define PORTF_MUX 0xFFC03210 /* Port F mux control */
-#define PORTG_MUX 0xFFC03214 /* Port G mux control */
-#define PORTH_MUX 0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
-#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
-#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
-#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
-#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
-#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
-#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
-#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
-
-#if 0
-#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
-
-#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
-#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
-#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
-#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
-#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
-#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
-
-#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
-#define IRQ_TWI 0x00000200 /* TWI Interrupt */
-#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
-#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
-#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
-#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
-#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
-#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
-
-#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
-#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
-#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
-#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
-#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
-#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
-#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
-#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
-#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
-#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
-
-#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
-#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
-#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
-#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
-#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
-#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
-#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
-#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
-#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
-#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
-#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
-#endif
-
-/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
-
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-
-/* **************** GENERAL PURPOSE TIMER MASKS **********************/
-/* TIMER_ENABLE Masks */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-#define TIMEN3 0x0008 /* Enable Timer 3 */
-#define TIMEN4 0x0010 /* Enable Timer 4 */
-#define TIMEN5 0x0020 /* Enable Timer 5 */
-#define TIMEN6 0x0040 /* Enable Timer 6 */
-#define TIMEN7 0x0080 /* Enable Timer 7 */
-
-/* TIMER_DISABLE Masks */
-#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
-#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
-#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
-#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
-#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
-#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
-#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
-#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
-
-/* TIMER_STATUS Masks */
-#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
-#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
-#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
-#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
-#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
-#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
-#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
-#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
-#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
-#define EXT_CLK 0x0003 /* External Clock Mode */
-#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
-#define PERIOD_CNT 0x0008 /* Period Count */
-#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
-#define TIN_SEL 0x0020 /* Timer Input Select */
-#define OUT_DIS 0x0040 /* Output Pad Disable */
-#define CLK_SEL 0x0080 /* Timer Clock Select */
-#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
-#define EMU_RUN 0x0200 /* Emulation Behavior Select */
-#define ERR_TYP 0xC000 /* Error Type */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
-#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
-#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
-#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
-#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
-#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
-#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
-
-#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
-#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
-#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
-#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
-#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
-#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
-#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
-#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
-#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
-#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
-#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
-#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
-#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
-
-#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
-#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
-#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
-#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
-#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
-#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
-#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
-
-
-/* ********************** SDRAM CONTROLLER MASKS **********************************************/
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SDRAM Signals */
-#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
-#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
-#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
-#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
-#define EBUFE 0x02000000 /* Enable External Buffering Timing */
-#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
-#define EMREN 0x10000000 /* Extended Mode Register Enable */
-#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
-#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x0001 /* Enable SDRAM External Bank */
-#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
-#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
-#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
-#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
-#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
-#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
-#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
-#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x0001 /* SDRAM Controller Idle */
-#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
-#define SDPUA 0x0004 /* SDRAM Power-Up Active */
-#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
-#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
-#define BGSTAT 0x0020 /* Bus Grant Status */
-
-
-/* ************************** DMA CONTROLLER MASKS ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
-#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
-#define PMAP_PPI 0x0000 /* PPI Port DMA */
-#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
-#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
-#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
-#define PMAP_SPI 0x7000 /* SPI Port DMA */
-#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
-#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
-#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
-#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
-
-/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* Omit CAN masks from defBF534.h */
-
-/* ******************* PIN CONTROL REGISTER MASKS ************************/
-/* PORT_MUX Masks */
-#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
-#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
-#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
-
-#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
-#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
-#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
-#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
-
-#define PFDE 0x0008 /* Port F DMA Request Enable */
-#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
-#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
-
-#define PFTE 0x0010 /* Port F Timer Enable */
-#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
-#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
-
-#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
-#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
-#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
-
-#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
-#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
-#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
-
-#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
-#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
-#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
-
-#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
-#define PFFE_TIMER 0x0000 /* Enable TMR2 */
-#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
-
-#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
-#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
-#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
-
-#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
-#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
-#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
-
-#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
-#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
-#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART PFDE_UART
-#define PGDE_DMA PFDE_DMA
-#define CKELOW SCKELOW
-
-/* ==== end from defBF534.h ==== */
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
-#define HOST_STATUS 0xffc03404 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
-
-/* Counter Registers */
-
-#define CNT_CONFIG 0xffc03500 /* Configuration Register */
-#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
-#define CNT_STATUS 0xffc03508 /* Status Register */
-#define CNT_COMMAND 0xffc0350c /* Command Register */
-#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
-#define CNT_COUNTER 0xffc03514 /* Counter Register */
-#define CNT_MAX 0xffc03518 /* Maximal Count Register */
-#define CNT_MIN 0xffc0351c /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
-#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
-#define SECURE_CONTROL 0xffc03624 /* Secure Control */
-#define SECURE_STATUS 0xffc03628 /* Secure Status */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* NFC Registers */
-
-#define NFC_CTL 0xffc03700 /* NAND Control Register */
-#define NFC_STAT 0xffc03704 /* NAND Status Register */
-#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
-#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
-#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
-#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
-#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
-#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
-#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
-#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
-#define NFC_READ 0xffc0372c /* NAND Read Data Register */
-#define NFC_ADDR 0xffc03740 /* NAND Address Register */
-#define NFC_CMD 0xffc03744 /* NAND Command Register */
-#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
-#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for HOST_CONTROL */
-
-#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
-#define HOST_CNTR_nHOST_EN 0x0
-#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
-#define HOST_CNTR_nHOST_END 0x0
-#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
-#define HOST_CNTR_nDATA_SIZE 0x0
-#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
-#define HOST_CNTR_nHOST_RST 0x0
-#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
-#define HOST_CNTR_nHRDY_OVR 0x0
-#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
-#define HOST_CNTR_nINT_MODE 0x0
-#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
-#define HOST_CNTR_ nBT_EN 0x0
-#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
-#define HOST_CNTR_nEHW 0x0
-#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
-#define HOST_CNTR_nEHR 0x0
-#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
-#define HOST_CNTR_nBDR 0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define HOST_STAT_READY 0x1 /* DMA Ready */
-#define HOST_STAT_nREADY 0x0
-#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
-#define HOST_STAT_nFIFOFULL 0x0
-#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
-#define HOST_STAT_nFIFOEMPTY 0x0
-#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
-#define HOST_STAT_nCOMPLETE 0x0
-#define HOST_STAT_HSHK 0x10 /* Host Handshake */
-#define HOST_STAT_nHSHK 0x0
-#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
-#define HOST_STAT_nTIMEOUT 0x0
-#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
-#define HOST_STAT_nHIRQ 0x0
-#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
-#define HOST_STAT_nALLOW_CNFG 0x0
-#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
-#define HOST_STAT_nDMA_DIR 0x0
-#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
-#define HOST_STAT_nBTE 0x0
-#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
-#define HOST_STAT_nHOSTRD_DONE 0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define EMUDABL 0x1 /* Emulation Disable. */
-#define nEMUDABL 0x0
-#define RSTDABL 0x2 /* Reset Disable */
-#define nRSTDABL 0x0
-#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
-#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
-#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
-#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
-#define nDMA0OVR 0x0
-#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
-#define nDMA1OVR 0x0
-#define EMUOVR 0x4000 /* Emulation Override */
-#define nEMUOVR 0x0
-#define OTPSEN 0x8000 /* OTP Secrets Enable. */
-#define nOTPSEN 0x0
-#define L2DABL 0x70000 /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define SECURE0 0x1 /* SECURE 0 */
-#define nSECURE0 0x0
-#define SECURE1 0x2 /* SECURE 1 */
-#define nSECURE1 0x0
-#define SECURE2 0x4 /* SECURE 2 */
-#define nSECURE2 0x0
-#define SECURE3 0x8 /* SECURE 3 */
-#define nSECURE3 0x0
-
-/* Bit masks for SECURE_STATUS */
-
-#define SECMODE 0x3 /* Secured Mode Control State */
-#define NMI 0x4 /* Non Maskable Interrupt */
-#define nNMI 0x0
-#define AFVALID 0x8 /* Authentication Firmware Valid */
-#define nAFVALID 0x0
-#define AFEXIT 0x10 /* Authentication Firmware Exit */
-#define nAFEXIT 0x0
-#define SECSTAT 0xe0 /* Secure Status */
-
-#endif /* _DEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h
deleted file mode 100644
index 591e00ff620a..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/defBF525.h
+++ /dev/null
@@ -1,678 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF525_H
-#define _DEF_BF525_H
-
-/* BF525 is BF522 + USB */
-#include "defBF522.h"
-
-/* USB Control Registers */
-
-#define USB_FADDR 0xffc03800 /* Function address register */
-#define USB_POWER 0xffc03804 /* Power management register */
-#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xffc03820 /* USB frame number */
-#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
-
-#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xffc03be0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xffc03be8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
-#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
-#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
-#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
-#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
-#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
-#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
-#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
-#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Bit masks for USB_FADDR */
-
-#define FUNCTION_ADDRESS 0x7f /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define nENABLE_SUSPENDM 0x0
-#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define nSUSPEND_MODE 0x0
-#define RESUME_MODE 0x4 /* DMA Mode */
-#define nRESUME_MODE 0x0
-#define RESET 0x8 /* Reset indicator */
-#define nRESET 0x0
-#define HS_MODE 0x10 /* High Speed mode indicator */
-#define nHS_MODE 0x0
-#define HS_ENABLE 0x20 /* high Speed Enable */
-#define nHS_ENABLE 0x0
-#define SOFT_CONN 0x40 /* Soft connect */
-#define nSOFT_CONN 0x0
-#define ISO_UPDATE 0x80 /* Isochronous update */
-#define nISO_UPDATE 0x0
-
-/* Bit masks for USB_INTRTX */
-
-#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define nEP0_TX 0x0
-#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define nEP1_TX 0x0
-#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define nEP2_TX 0x0
-#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define nEP3_TX 0x0
-#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define nEP4_TX 0x0
-#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define nEP5_TX 0x0
-#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define nEP6_TX 0x0
-#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-#define nEP7_TX 0x0
-
-/* Bit masks for USB_INTRRX */
-
-#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define nEP1_RX 0x0
-#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define nEP2_RX 0x0
-#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define nEP3_RX 0x0
-#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define nEP4_RX 0x0
-#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define nEP5_RX 0x0
-#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define nEP6_RX 0x0
-#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-#define nEP7_RX 0x0
-
-/* Bit masks for USB_INTRTXE */
-
-#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define nEP0_TX_E 0x0
-#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
-#define nEP1_TX_E 0x0
-#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
-#define nEP2_TX_E 0x0
-#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
-#define nEP3_TX_E 0x0
-#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
-#define nEP4_TX_E 0x0
-#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
-#define nEP5_TX_E 0x0
-#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
-#define nEP6_TX_E 0x0
-#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
-#define nEP7_TX_E 0x0
-
-/* Bit masks for USB_INTRRXE */
-
-#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
-#define nEP1_RX_E 0x0
-#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
-#define nEP2_RX_E 0x0
-#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
-#define nEP3_RX_E 0x0
-#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
-#define nEP4_RX_E 0x0
-#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
-#define nEP5_RX_E 0x0
-#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
-#define nEP6_RX_E 0x0
-#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
-#define nEP7_RX_E 0x0
-
-/* Bit masks for USB_INTRUSB */
-
-#define SUSPEND_B 0x1 /* Suspend indicator */
-#define nSUSPEND_B 0x0
-#define RESUME_B 0x2 /* Resume indicator */
-#define nRESUME_B 0x0
-#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
-#define nRESET_OR_BABLE_B 0x0
-#define SOF_B 0x8 /* Start of frame */
-#define nSOF_B 0x0
-#define CONN_B 0x10 /* Connection indicator */
-#define nCONN_B 0x0
-#define DISCON_B 0x20 /* Disconnect indicator */
-#define nDISCON_B 0x0
-#define SESSION_REQ_B 0x40 /* Session Request */
-#define nSESSION_REQ_B 0x0
-#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-#define nVBUS_ERROR_B 0x0
-
-/* Bit masks for USB_INTRUSBE */
-
-#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
-#define nSUSPEND_BE 0x0
-#define RESUME_BE 0x2 /* Resume indicator int enable */
-#define nRESUME_BE 0x0
-#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
-#define nRESET_OR_BABLE_BE 0x0
-#define SOF_BE 0x8 /* Start of frame int enable */
-#define nSOF_BE 0x0
-#define CONN_BE 0x10 /* Connection indicator int enable */
-#define nCONN_BE 0x0
-#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define nDISCON_BE 0x0
-#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define nSESSION_REQ_BE 0x0
-#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-#define nVBUS_ERROR_BE 0x0
-
-/* Bit masks for USB_FRAME */
-
-#define FRAME_NUMBER 0x7ff /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define SELECTED_ENDPOINT 0xf /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define GLOBAL_ENA 0x1 /* enables USB module */
-#define nGLOBAL_ENA 0x0
-#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
-#define nEP1_TX_ENA 0x0
-#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
-#define nEP2_TX_ENA 0x0
-#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
-#define nEP3_TX_ENA 0x0
-#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
-#define nEP4_TX_ENA 0x0
-#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
-#define nEP5_TX_ENA 0x0
-#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
-#define nEP6_TX_ENA 0x0
-#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
-#define nEP7_TX_ENA 0x0
-#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
-#define nEP1_RX_ENA 0x0
-#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
-#define nEP2_RX_ENA 0x0
-#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
-#define nEP3_RX_ENA 0x0
-#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
-#define nEP4_RX_ENA 0x0
-#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define nEP5_RX_ENA 0x0
-#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define nEP6_RX_ENA 0x0
-#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-#define nEP7_RX_ENA 0x0
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define SESSION 0x1 /* session indicator */
-#define nSESSION 0x0
-#define HOST_REQ 0x2 /* Host negotiation request */
-#define nHOST_REQ 0x0
-#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define nHOST_MODE 0x0
-#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define nVBUS0 0x0
-#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define nVBUS1 0x0
-#define LSDEV 0x20 /* Low-speed indicator */
-#define nLSDEV 0x0
-#define FSDEV 0x40 /* Full or High-speed indicator */
-#define nFSDEV 0x0
-#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-#define nB_DEVICE 0x0
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define nDRIVE_VBUS_ON 0x0
-#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define nDRIVE_VBUS_OFF 0x0
-#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define nCHRG_VBUS_START 0x0
-#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define nCHRG_VBUS_END 0x0
-#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define nDISCHRG_VBUS_START 0x0
-#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-#define nDISCHRG_VBUS_END 0x0
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
-#define nDRIVE_VBUS_ON_ENA 0x0
-#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
-#define nDRIVE_VBUS_OFF_ENA 0x0
-#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
-#define nCHRG_VBUS_START_ENA 0x0
-#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
-#define nCHRG_VBUS_END_ENA 0x0
-#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define nDISCHRG_VBUS_START_ENA 0x0
-#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-#define nDISCHRG_VBUS_END_ENA 0x0
-
-/* Bit masks for USB_CSR0 */
-
-#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define nRXPKTRDY 0x0
-#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define nTXPKTRDY 0x0
-#define STALL_SENT 0x4 /* STALL handshake sent */
-#define nSTALL_SENT 0x0
-#define DATAEND 0x8 /* Data end indicator */
-#define nDATAEND 0x0
-#define SETUPEND 0x10 /* Setup end */
-#define nSETUPEND 0x0
-#define SENDSTALL 0x20 /* Send STALL handshake */
-#define nSENDSTALL 0x0
-#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define nSERVICED_RXPKTRDY 0x0
-#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define nSERVICED_SETUPEND 0x0
-#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define nFLUSHFIFO 0x0
-#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define nSTALL_RECEIVED_H 0x0
-#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define nSETUPPKT_H 0x0
-#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define nERROR_H 0x0
-#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define nREQPKT_H 0x0
-#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define nSTATUSPKT_H 0x0
-#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-#define nNAK_TIMEOUT_H 0x0
-
-/* Bit masks for USB_COUNT0 */
-
-#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define nTXPKTRDY_T 0x0
-#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define nFIFO_NOT_EMPTY_T 0x0
-#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define nUNDERRUN_T 0x0
-#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define nFLUSHFIFO_T 0x0
-#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define nSTALL_SEND_T 0x0
-#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define nSTALL_SENT_T 0x0
-#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define nCLEAR_DATATOGGLE_T 0x0
-#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define nINCOMPTX_T 0x0
-#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define nDMAREQMODE_T 0x0
-#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define nFORCE_DATATOGGLE_T 0x0
-#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define nDMAREQ_ENA_T 0x0
-#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define nISO_T 0x0
-#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define nAUTOSET_T 0x0
-#define ERROR_TH 0x4 /* error condition host mode */
-#define nERROR_TH 0x0
-#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define nSTALL_RECEIVED_TH 0x0
-#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-#define nNAK_TIMEOUT_TH 0x0
-
-/* Bit masks for USB_TXCOUNT */
-
-#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define nRXPKTRDY_R 0x0
-#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define nFIFO_FULL_R 0x0
-#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define nOVERRUN_R 0x0
-#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define nDATAERROR_R 0x0
-#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define nFLUSHFIFO_R 0x0
-#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define nSTALL_SEND_R 0x0
-#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define nSTALL_SENT_R 0x0
-#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define nCLEAR_DATATOGGLE_R 0x0
-#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define nINCOMPRX_R 0x0
-#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define nDMAREQMODE_R 0x0
-#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define nDISNYET_R 0x0
-#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define nDMAREQ_ENA_R 0x0
-#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define nISO_R 0x0
-#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define nAUTOCLEAR_R 0x0
-#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define nERROR_RH 0x0
-#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define nREQPKT_RH 0x0
-#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define nSTALL_RECEIVED_RH 0x0
-#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
-#define nINCOMPRX_RH 0x0
-#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define nDMAREQMODE_RH 0x0
-#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-#define nAUTOREQ_RH 0x0
-
-/* Bit masks for USB_RXCOUNT */
-
-#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define TARGET_EP_NO_T 0xf /* EP number */
-#define PROTOCOL_T 0xc /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define TARGET_EP_NO_R 0xf /* EP number */
-#define PROTOCOL_R 0xc /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define nDMA0_INT 0x0
-#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define nDMA1_INT 0x0
-#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define nDMA2_INT 0x0
-#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define nDMA3_INT 0x0
-#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define nDMA4_INT 0x0
-#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define nDMA5_INT 0x0
-#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define nDMA6_INT 0x0
-#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-#define nDMA7_INT 0x0
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define DMA_ENA 0x1 /* DMA enable */
-#define nDMA_ENA 0x0
-#define DIRECTION 0x2 /* direction of DMA transfer */
-#define nDIRECTION 0x0
-#define MODE 0x4 /* DMA Bus error */
-#define nMODE 0x0
-#define INT_ENA 0x8 /* Interrupt enable */
-#define nINT_ENA 0x0
-#define EPNUM 0xf0 /* EP number */
-#define BUSERROR 0x100 /* DMA Bus error */
-#define nBUSERROR 0x0
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#endif /* _DEF_BF525_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h
deleted file mode 100644
index aeb84795b35e..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/defBF527.h
+++ /dev/null
@@ -1,391 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF527_H
-#define _DEF_BF527_H
-
-/* BF527 is BF525 + EMAC */
-#include "defBF525.h"
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-/* Listing for IEEE-Supported Count Registers */
-
-#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
-#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
-#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
-#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
-#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
-#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
-#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
-#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
-#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
-#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
-#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
-#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
-#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
-#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
-#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
-#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
-#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
-#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
-#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
-#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
-#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
-#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
-#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
-#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
-#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
-#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
-#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
-#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
-#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
-#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
-#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
-#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
-#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
-#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
-
-/* EMAC_OPMODE Masks */
-
-#define RE 0x00000001 /* Receiver Enable */
-#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
-#define HU 0x00000010 /* Hash Filter Unicast Address */
-#define HM 0x00000020 /* Hash Filter Multicast Address */
-#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
-#define PR 0x00000080 /* Promiscuous Mode Enable */
-#define IFE 0x00000100 /* Inverse Filtering Enable */
-#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
-#define PBF 0x00000400 /* Pass Bad Frames Enable */
-#define PSF 0x00000800 /* Pass Short Frames Enable */
-#define RAF 0x00001000 /* Receive-All Mode */
-#define TE 0x00010000 /* Transmitter Enable */
-#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
-#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
-#define DC 0x00080000 /* Deferral Check */
-#define BOLMT 0x00300000 /* Back-Off Limit */
-#define BOLMT_10 0x00000000 /* 10-bit range */
-#define BOLMT_8 0x00100000 /* 8-bit range */
-#define BOLMT_4 0x00200000 /* 4-bit range */
-#define BOLMT_1 0x00300000 /* 1-bit range */
-#define DRTY 0x00400000 /* Disable TX Retry On Collision */
-#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
-#define RMII 0x01000000 /* RMII/MII* Mode */
-#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
-#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
-#define LB 0x08000000 /* Internal Loopback Enable */
-#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
-
-/* EMAC_STAADD Masks */
-
-#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
-#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
-#define STADISPRE 0x00000004 /* Disable Preamble Generation */
-#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
-#define REGAD 0x000007C0 /* STA Register Address */
-#define PHYAD 0x0000F800 /* PHY Device Address */
-
-#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
-#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
-
-/* EMAC_STADAT Mask */
-
-#define STADATA 0x0000FFFF /* Station Management Data */
-
-/* EMAC_FLC Masks */
-
-#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
-#define FLCE 0x00000002 /* Flow Control Enable */
-#define PCF 0x00000004 /* Pass Control Frames */
-#define BKPRSEN 0x00000008 /* Enable Backpressure */
-#define FLCPAUSE 0xFFFF0000 /* Pause Time */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
-
-/* EMAC_WKUP_CTL Masks */
-
-#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
-#define MPKE 0x00000002 /* Magic Packet Enable */
-#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
-#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
-#define MPKS 0x00000020 /* Magic Packet Received Status */
-#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
-
-/* EMAC_WKUP_FFCMD Masks */
-
-#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
-#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
-#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
-#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
-#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
-#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
-#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
-#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
-
-/* EMAC_WKUP_FFOFF Masks */
-
-#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
-#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
-#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
-#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
-#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-
-#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
-#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-
-#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
-#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
-
-/* EMAC_SYSCTL Masks */
-
-#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
-#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
-#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
-#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
-#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
-
-#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
-
-/* EMAC_SYSTAT Masks */
-
-#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
-#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
-#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
-#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
-#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
-#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
-#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
-#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-
-#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
-#define RX_COMP 0x00001000 /* RX Frame Complete */
-#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
-#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
-#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
-#define RX_CRC 0x00010000 /* RX Frame CRC Error */
-#define RX_LEN 0x00020000 /* RX Frame Length Error */
-#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
-#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
-#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
-#define RX_PHY 0x00200000 /* RX Frame PHY Error */
-#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
-#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
-#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
-#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
-#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
-#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
-#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
-#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
-#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
-#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
-
-/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
-
-#define TX_COMP 0x00000001 /* TX Frame Complete */
-#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
-#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
-#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
-#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
-#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
-#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
-#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
-#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
-#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
-#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
-#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
-#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
-#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
-#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC 0x00000001 /* Reset All Counters */
-#define CROLL 0x00000002 /* Counter Roll-Over Enable */
-#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
-#define MMCE 0x00000008 /* Enable MMC Counter Operation */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
-#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
-#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
-#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
-#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
-#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
-#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
-#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
-#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
-#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
-#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
-#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
-#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
-#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
-#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
-#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
-#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
-#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
-#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
-#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
-#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
-#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
-#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
-#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
-
-#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
-#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
-#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
-#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
-#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
-#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
-#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
-#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
-#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
-#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
-#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
-#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
-#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
-#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
-#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
-#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
-#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
-#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
-#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
-#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
-#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
-#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
-#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
-
-#endif /* _DEF_BF527_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/dma.h b/arch/blackfin/mach-bf527/include/mach/dma.h
deleted file mode 100644
index eb287da101a2..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/dma.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 16
-
-#define CH_PPI 0 /* PPI receive/transmit or NFC */
-#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
-#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */
-#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */
-#define CH_SPORT0_RX 3 /* SPORT0 receive */
-#define CH_SPORT0_TX 4 /* SPORT0 transmit */
-#define CH_SPORT1_RX 5 /* SPORT1 receive */
-#define CH_SPORT1_TX 6 /* SPORT1 transmit */
-#define CH_SPI 7 /* SPI transmit/receive */
-#define CH_UART0_RX 8 /* UART0 receive */
-#define CH_UART0_TX 9 /* UART0 transmit */
-#define CH_UART1_RX 10 /* UART1 receive */
-#define CH_UART1_TX 11 /* UART1 transmit */
-
-#define CH_MEM_STREAM0_DEST 12 /* TX */
-#define CH_MEM_STREAM0_SRC 13 /* RX */
-#define CH_MEM_STREAM1_DEST 14 /* TX */
-#define CH_MEM_STREAM1_SRC 15 /* RX */
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define CH_NFC CH_PPI /* PPI receive/transmit or NFC */
-#elif defined(CONFIG_BF527_NAND_D_PORTH)
-#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/gpio.h b/arch/blackfin/mach-bf527/include/mach/gpio.h
deleted file mode 100644
index fba606b699c3..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/gpio.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-#define GPIO_PH3 35
-#define GPIO_PH4 36
-#define GPIO_PH5 37
-#define GPIO_PH6 38
-#define GPIO_PH7 39
-#define GPIO_PH8 40
-#define GPIO_PH9 41
-#define GPIO_PH10 42
-#define GPIO_PH11 43
-#define GPIO_PH12 44
-#define GPIO_PH13 45
-#define GPIO_PH14 46
-#define GPIO_PH15 47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h
deleted file mode 100644
index ed7310ff819b..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/irq.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF527_IRQ_H_
-#define _BF527_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
-#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
-#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
-#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
-#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
-#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
-#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
-#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
-#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
-#define IRQ_RTC BFIN_IRQ(14) /* RTC */
-#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
-#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(20) /* TWI */
-#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
-#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
-#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
-#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
-#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
-#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
-#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
-#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
-#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
-#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
-#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
-#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
-#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
-#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
-#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
-#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
-#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
-#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
-#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
-#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
-#define IRQ_SPI_ERROR BFIN_IRQ(47) /* SPI Status */
-#define IRQ_NFC_ERROR BFIN_IRQ(48) /* NAND Error */
-#define IRQ_HDMA_ERROR BFIN_IRQ(49) /* HDMA Error */
-#define IRQ_HDMA BFIN_IRQ(50) /* HDMA (TFI) */
-#define IRQ_USB_EINT BFIN_IRQ(51) /* USB_EINT Interrupt */
-#define IRQ_USB_INT0 BFIN_IRQ(52) /* USB_INT0 Interrupt */
-#define IRQ_USB_INT1 BFIN_IRQ(53) /* USB_INT1 Interrupt */
-#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
-#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
-
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
-
-#define IRQ_PG0 87
-#define IRQ_PG1 88
-#define IRQ_PG2 89
-#define IRQ_PG3 90
-#define IRQ_PG4 91
-#define IRQ_PG5 92
-#define IRQ_PG6 93
-#define IRQ_PG7 94
-#define IRQ_PG8 95
-#define IRQ_PG9 96
-#define IRQ_PG10 97
-#define IRQ_PG11 98
-#define IRQ_PG12 99
-#define IRQ_PG13 100
-#define IRQ_PG14 101
-#define IRQ_PG15 102
-
-#define IRQ_PH0 103
-#define IRQ_PH1 104
-#define IRQ_PH2 105
-#define IRQ_PH3 106
-#define IRQ_PH4 107
-#define IRQ_PH5 108
-#define IRQ_PH6 109
-#define IRQ_PH7 110
-#define IRQ_PH8 111
-#define IRQ_PH9 112
-#define IRQ_PH10 113
-#define IRQ_PH11 114
-#define IRQ_PH12 115
-#define IRQ_PH13 116
-#define IRQ_PH14 117
-#define IRQ_PH15 118
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
-
-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_DMAR0_BLK_POS 8
-#define IRQ_DMAR1_BLK_POS 12
-#define IRQ_DMAR0_OVR_POS 16
-#define IRQ_DMAR1_OVR_POS 20
-#define IRQ_PPI_ERROR_POS 24
-#define IRQ_MAC_ERROR_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPORT0_ERROR_POS 0
-#define IRQ_SPORT1_ERROR_POS 4
-#define IRQ_UART0_ERROR_POS 16
-#define IRQ_UART1_ERROR_POS 20
-#define IRQ_RTC_POS 24
-#define IRQ_PPI_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_SPORT0_RX_POS 0
-#define IRQ_SPORT0_TX_POS 4
-#define IRQ_SPORT1_RX_POS 8
-#define IRQ_SPORT1_TX_POS 12
-#define IRQ_TWI_POS 16
-#define IRQ_SPI_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS 0
-#define IRQ_UART1_TX_POS 4
-#define IRQ_OPTSEC_POS 8
-#define IRQ_CNT_POS 12
-#define IRQ_MAC_RX_POS 16
-#define IRQ_PORTH_INTA_POS 20
-#define IRQ_MAC_TX_POS 24
-#define IRQ_PORTH_INTB_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_TIMER0_POS 0
-#define IRQ_TIMER1_POS 4
-#define IRQ_TIMER2_POS 8
-#define IRQ_TIMER3_POS 12
-#define IRQ_TIMER4_POS 16
-#define IRQ_TIMER5_POS 20
-#define IRQ_TIMER6_POS 24
-#define IRQ_TIMER7_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_PORTG_INTA_POS 0
-#define IRQ_PORTG_INTB_POS 4
-#define IRQ_MEM_DMA0_POS 8
-#define IRQ_MEM_DMA1_POS 12
-#define IRQ_WATCH_POS 16
-#define IRQ_PORTF_INTA_POS 20
-#define IRQ_PORTF_INTB_POS 24
-#define IRQ_SPI_ERROR_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_NFC_ERROR_POS 0
-#define IRQ_HDMA_ERROR_POS 4
-#define IRQ_HDMA_POS 8
-#define IRQ_USB_EINT_POS 12
-#define IRQ_USB_INT0_POS 16
-#define IRQ_USB_INT1_POS 20
-#define IRQ_USB_INT2_POS 24
-#define IRQ_USB_DMA_POS 28
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/mem_map.h b/arch/blackfin/mach-bf527/include/mach/mem_map.h
deleted file mode 100644
index d96e894afd2c..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/mem_map.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * BF52x memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x8000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF527 ADSP-BF525 ADSP-BF522 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE */
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/pll.h b/arch/blackfin/mach-bf527/include/mach/pll.h
deleted file mode 100644
index 94cca674d835..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf527/include/mach/portmux.h b/arch/blackfin/mach-bf527/include/mach/portmux.h
deleted file mode 100644
index 08bae421f5c9..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/portmux.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#if defined(CONFIG_BF527_SPORT0_PORTF)
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#elif defined(CONFIG_BF527_SPORT0_PORTG)
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#if defined(CONFIG_BF527_SPORT0_TSCLK_PG10)
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#elif defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#endif
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#endif
-
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_UART1_PORTF)
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#elif defined(CONFIG_BF527_UART1_PORTG)
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#endif
-
-#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3))
-#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3))
-#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3))
-
-#define P_HWAIT (P_DONTCARE)
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-/* #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_MDC (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-
-#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#elif defined(CONFIG_BF527_NAND_D_PORTH)
-#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#endif
-
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_NAND_WE (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_NAND_RE (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_NAND_CLE (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_NAND_ALE (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-
-#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
-#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
-#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
-#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
-#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
-#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
-#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
-#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
-
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
-#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
-#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
-#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
-#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
-#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_MDIO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_TMR0 (P_DONTCARE)
-#define P_TMRCLK (P_DONTCARE)
-#define P_PPI0_CLK (P_DONTCARE)
-
-#define P_MII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_ERxER, \
- P_MII0_CRS, \
- P_MDC, \
- P_MDIO, 0}
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_RMII0_REF_CLK, \
- P_RMII0_MDINT, \
- P_RMII0_CRS_DV, \
- P_MDC, \
- P_MDIO, 0}
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf527/ints-priority.c b/arch/blackfin/mach-bf527/ints-priority.c
deleted file mode 100644
index 44ca215bf164..000000000000
--- a/arch/blackfin/mach-bf527/ints-priority.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
- ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
- ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
- ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
- ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
- ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
- ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
-
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
- ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
- ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
- ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
- ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
- ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
- ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
- ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
- ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
- ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
- ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
- ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
- ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
- ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
- ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
- ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
- ((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_NFC_ERROR - 7) << IRQ_NFC_ERROR_POS) |
- ((CONFIG_IRQ_HDMA_ERROR - 7) << IRQ_HDMA_ERROR_POS) |
- ((CONFIG_IRQ_HDMA - 7) << IRQ_HDMA_POS) |
- ((CONFIG_IRQ_USB_EINT - 7) << IRQ_USB_EINT_POS) |
- ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
- ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
- ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
- ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS));
-
- SSYNC();
-}