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| author | Jiri Kosina <jkosina@suse.cz> | 2010-08-10 13:22:08 +0200 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2010-08-10 13:22:08 +0200 |
| commit | fb8231a8b139035476f2a8aaac837d0099b66dad (patch) | |
| tree | 2875806beb96ea0cdab292146767a5085721dc6a /arch/blackfin/mach-bf548/include/mach/defBF544.h | |
| parent | fix printk typo 'faild' (diff) | |
| parent | Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6 (diff) | |
| download | linux-fb8231a8b139035476f2a8aaac837d0099b66dad.tar.xz linux-fb8231a8b139035476f2a8aaac837d0099b66dad.zip | |
Merge branch 'master' into for-next
Conflicts:
arch/arm/mach-omap1/board-nokia770.c
Diffstat (limited to 'arch/blackfin/mach-bf548/include/mach/defBF544.h')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF544.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h index f916c52a148a..e2771094de02 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF544.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h @@ -60,15 +60,15 @@ #define TWI1_REGBASE 0xffc02200 #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ -#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ +#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */ #define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ #define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ -#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ +#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */ #define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ #define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ #define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ #define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ -#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ +#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */ #define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ #define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ #define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ |