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| author | Sonic Zhang <sonic.zhang@analog.com> | 2008-01-27 09:32:31 +0100 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2008-01-27 09:32:31 +0100 |
| commit | 971d5bc4e5c75bfc4466deaff09839cd6f918eca (patch) | |
| tree | 1a3259e1c00c519e71e0f0842de3ec257781482c /arch/blackfin/mach-bf548 | |
| parent | [Blackfin] arch: Clean up dump_bfin_mem (diff) | |
| download | linux-971d5bc4e5c75bfc4466deaff09839cd6f918eca.tar.xz linux-971d5bc4e5c75bfc4466deaff09839cd6f918eca.zip | |
[Blackfin] arch: Fix bug to Enable bf548 to Re-program Clocks while Kernel boots.
Reprogram DDR EBIU register properly for bf548.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-bf548')
| -rw-r--r-- | arch/blackfin/mach-bf548/head.S | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S index 745662e88759..74fe258421a5 100644 --- a/arch/blackfin/mach-bf548/head.S +++ b/arch/blackfin/mach-bf548/head.S @@ -324,12 +324,25 @@ ENTRY(_start_dma_code) w[p0] = r0.l; ssync; +#if defined(CONFIG_BF54x) + P2.H = hi(EBIU_RSTCTL); + P2.L = lo(EBIU_RSTCTL); + R0 = [P2]; + BITSET (R0, 3); +#else P2.H = hi(EBIU_SDGCTL); P2.L = lo(EBIU_SDGCTL); R0 = [P2]; BITSET (R0, 24); +#endif [P2] = R0; SSYNC; +#if defined(CONFIG_BF54x) +.LSRR_MODE: + R0 = [P2]; + CC = BITTST(R0, 4); + if !CC JUMP .LSRR_MODE; +#endif r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ r0 = r0 << 9; /* Shift it over, */ @@ -361,6 +374,39 @@ ENTRY(_start_dma_code) w[p0] = r0.l; ssync; +#if defined(CONFIG_BF54x) + P2.H = hi(EBIU_RSTCTL); + P2.L = lo(EBIU_RSTCTL); + R0 = [P2]; + CC = BITTST(R0, 0); + if CC jump .Lskipddrrst; + BITSET (R0, 0); +.Lskipddrrst: + BITCLR (R0, 3); + [P2] = R0; + SSYNC; + + p0.l = lo(EBIU_DDRCTL0); + p0.h = hi(EBIU_DDRCTL0); + r0.l = lo(mem_DDRCTL0); + r0.h = hi(mem_DDRCTL0); + [p0] = r0; + ssync; + + p0.l = lo(EBIU_DDRCTL1); + p0.h = hi(EBIU_DDRCTL1); + r0.l = lo(mem_DDRCTL1); + r0.h = hi(mem_DDRCTL1); + [p0] = r0; + ssync; + + p0.l = lo(EBIU_DDRCTL2); + p0.h = hi(EBIU_DDRCTL2); + r0.l = lo(mem_DDRCTL2); + r0.h = hi(mem_DDRCTL2); + [p0] = r0; + ssync; +#else p0.l = lo(EBIU_SDRRC); p0.h = hi(EBIU_SDRRC); r0 = mem_SDRRC; @@ -394,6 +440,7 @@ ENTRY(_start_dma_code) R1 = R1 | R0; [P2] = R1; SSYNC; +#endif p0.h = hi(SIC_IWR0); p0.l = lo(SIC_IWR0); |