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| author | Mark Salter <msalter@redhat.com> | 2011-11-05 15:57:40 +0100 |
|---|---|---|
| committer | Mark Salter <msalter@redhat.com> | 2012-01-08 21:12:17 +0100 |
| commit | 25b48ff852e2e71b0d44d8ee6f69c9b704bd5070 (patch) | |
| tree | ee48a9e41d4cdeffcbb68b50261576887357e7a2 /arch/c6x | |
| parent | C6X: fix layout of EMIFA registers (diff) | |
| download | linux-25b48ff852e2e71b0d44d8ee6f69c9b704bd5070.tar.xz linux-25b48ff852e2e71b0d44d8ee6f69c9b704bd5070.zip | |
C6X: fix timer64 initialization
Some SoCs have a timer block enable controlled through the DSCR registers.
There is a problem in the timer64 driver initialization where the code
accesses a timer register to get the divisor used to calculate timer clock
rate. If the timer block has not been enabled when this register read takes
place, an exception is generated. This patch makes sure that the timer block
is enabled before accessing the registers.
Signed-off-by: Mark Salter <msalter@redhat.com>
Diffstat (limited to 'arch/c6x')
| -rw-r--r-- | arch/c6x/platforms/timer64.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/c6x/platforms/timer64.c b/arch/c6x/platforms/timer64.c index 783415861dae..03c03c249191 100644 --- a/arch/c6x/platforms/timer64.c +++ b/arch/c6x/platforms/timer64.c @@ -215,9 +215,17 @@ void __init timer64_init(void) /* If there is a device state control, save the ID. */ err = of_property_read_u32(np, "ti,dscr-dev-enable", &val); - if (!err) + if (!err) { timer64_devstate_id = val; + /* + * It is necessary to enable the timer block here because + * the TIMER_DIVISOR macro needs to read a timer register + * to get the divisor. + */ + dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_ENABLED); + } + pr_debug("%s: Timer irq=%d.\n", np->full_name, cd->irq); clockevents_calc_mult_shift(cd, c6x_core_freq / TIMER_DIVISOR, 5); |