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authorLaurent Pinchart <laurent.pinchart@ideasonboard.com>2013-05-15 16:36:19 +0200
committerMauro Carvalho Chehab <mchehab@osg.samsung.com>2015-04-03 05:59:49 +0200
commitdf3305156f989339529b3d6744b898d498fb1f7b (patch)
tree4f55b5f60cc68ff11a75c8e7574ddaff92a21034 /arch/c6x
parent[media] v4l: of: Add v4l2_of_parse_link() function (diff)
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[media] v4l: xilinx: Add Xilinx Video IP core
Xilinx platforms have no hardwired video capture or video processing interface. Users create capture and memory to memory processing pipelines in the FPGA fabric to suit their particular needs, by instantiating video IP cores from a large library. The Xilinx Video IP core is a framework that models a video pipeline described in the device tree and expose the pipeline to userspace through the media controller and V4L2 APIs. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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