diff options
| author | Guo Ren <ren_guo@c-sky.com> | 2018-09-05 08:25:10 +0200 |
|---|---|---|
| committer | Guo Ren <ren_guo@c-sky.com> | 2018-10-25 17:36:19 +0200 |
| commit | 00a9730e1007c6cc87a7c78af2f24a4105d616ee (patch) | |
| tree | c014e5a0606a7a88b6e3493f49862c040f9aeea8 /arch/csky/mm/syscache.c | |
| parent | csky: System Call (diff) | |
| download | linux-00a9730e1007c6cc87a7c78af2f24a4105d616ee.tar.xz linux-00a9730e1007c6cc87a7c78af2f24a4105d616ee.zip | |
csky: Cache and TLB routines
This patch adds cache and tlb sync codes for abiv1 & abiv2.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/csky/mm/syscache.c')
| -rw-r--r-- | arch/csky/mm/syscache.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/csky/mm/syscache.c b/arch/csky/mm/syscache.c new file mode 100644 index 000000000000..c4645e4e97f4 --- /dev/null +++ b/arch/csky/mm/syscache.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. + +#include <linux/syscalls.h> +#include <asm/page.h> +#include <asm/cache.h> +#include <asm/cachectl.h> + +SYSCALL_DEFINE3(cacheflush, + void __user *, addr, + unsigned long, bytes, + int, cache) +{ + switch (cache) { + case ICACHE: + icache_inv_range((unsigned long)addr, + (unsigned long)addr + bytes); + break; + case DCACHE: + dcache_wb_range((unsigned long)addr, + (unsigned long)addr + bytes); + break; + case BCACHE: + cache_wbinv_range((unsigned long)addr, + (unsigned long)addr + bytes); + break; + default: + return -EINVAL; + } + + return 0; +} |