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authorPatrice Chotard <patrice.chotard@st.com>2020-06-18 19:24:56 +0200
committerArnd Bergmann <arnd@arndb.de>2020-06-28 14:46:54 +0200
commit0f77ce26ebcf6ea384421d2dd47b924b83649692 (patch)
tree99dd5a9129118c58cc01d28a643ede9421783950 /arch/csky/mm
parentMerge tag 'tee-ml-for-v5.8' of git://git.linaro.org/people/jens.wiklander/lin... (diff)
downloadlinux-0f77ce26ebcf6ea384421d2dd47b924b83649692.tar.xz
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Revert "ARM: sti: Implement dummy L2 cache's write_sec"
This reverts commit 7b8e0188fa717cd9abc4fb52587445b421835c2a. Initially, STiH410-B2260 was supposed to be secured, that's why l2c_write_sec was stubbed to avoid secure register access from non secure world. But by default, STiH410-B2260 is running in non secure mode, so L2 cache register accesses are authorized, l2c_write_sec stub is not needed. With this patch, L2 cache is configured and performance are enhanced. Link: https://lore.kernel.org/r/20200618172456.29475-1-patrice.chotard@st.com Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Cc: Alain Volmat <alain.volmat@st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/csky/mm')
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