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authorJitao Shi <jitao.shi@mediatek.com>2016-11-16 04:20:54 +0100
committerCK Hu <ck.hu@mediatek.com>2016-11-24 07:53:14 +0100
commitf6c872397028837c80685ee96c4011c62abe9a73 (patch)
tree47927838d25847c3dee50bb8c420d760c70a7373 /arch/frv
parentdrm/mediatek: fix a typo of DISP_OD_CFG to OD_RELAYMODE (diff)
downloadlinux-f6c872397028837c80685ee96c4011c62abe9a73.tar.xz
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drm/mediatek: fixed the calc method of data rate per lane
Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e. Tlpx, Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP mode, those signals will cause h-time larger than normal and reduce FPS. So need to multiply a coefficient to offset the extra signal's effect. coefficient = ((htotal*bpp/lane_number)+Tlpx+Ths_prep+Ths_zero+ Ths_trail+Ths_exit)/(htotal*bpp/lane_number) Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
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