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| author | Zachary Amsden <zach@vmware.com> | 2005-09-04 00:56:36 +0200 |
|---|---|---|
| committer | Linus Torvalds <torvalds@evo.osdl.org> | 2005-09-05 09:06:11 +0200 |
| commit | 4bb0d3ec3e5b1e9e2399cdc641b3b6521ac9cdaa (patch) | |
| tree | 5e8d7646f5c6a2cec990b6d591f230d496b20664 /arch/i386/mm/pageattr.c | |
| parent | [PATCH] i386: clean up vDSO alignment padding (diff) | |
| download | linux-4bb0d3ec3e5b1e9e2399cdc641b3b6521ac9cdaa.tar.xz linux-4bb0d3ec3e5b1e9e2399cdc641b3b6521ac9cdaa.zip | |
[PATCH] i386: inline asm cleanup
i386 Inline asm cleanup. Use cr/dr accessor functions.
Also, a potential bugfix. Also, some CR accessors really should be volatile.
Reads from CR0 (numeric state may change in an exception handler), writes to
CR4 (flipping CR4.TSD) and reads from CR2 (page fault) prevent instruction
re-ordering. I did not add memory clobber to CR3 / CR4 / CR0 updates, as it
was not there to begin with, and in no case should kernel memory be clobbered,
except when doing a TLB flush, which already has memory clobber.
I noticed that page invalidation does not have a memory clobber. I can't find
a bug as a result, but there is definitely a potential for a bug here:
#define __flush_tlb_single(addr) \
__asm__ __volatile__("invlpg %0": :"m" (*(char *) addr))
Signed-off-by: Zachary Amsden <zach@vmware.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/i386/mm/pageattr.c')
| -rw-r--r-- | arch/i386/mm/pageattr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/i386/mm/pageattr.c b/arch/i386/mm/pageattr.c index cb3da6baa704..bce06a79eafa 100644 --- a/arch/i386/mm/pageattr.c +++ b/arch/i386/mm/pageattr.c @@ -62,7 +62,7 @@ static void flush_kernel_map(void *dummy) { /* Could use CLFLUSH here if the CPU supports it (Hammer,P4) */ if (boot_cpu_data.x86_model >= 4) - asm volatile("wbinvd":::"memory"); + wbinvd(); /* Flush all to work around Errata in early athlons regarding * large page flushing. */ |