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| author | Russ Anderson <rja@sgi.com> | 2006-11-06 23:45:18 +0100 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2006-12-07 20:10:16 +0100 |
| commit | 5b4d5681ffaa6e1bf3b085beb701d87c7c7404da (patch) | |
| tree | 2db8dfeb74989741039242bb734a57e79caaf176 /arch/ia64/lib | |
| parent | [IA64] Update processor_info features (diff) | |
| download | linux-5b4d5681ffaa6e1bf3b085beb701d87c7c7404da.tar.xz linux-5b4d5681ffaa6e1bf3b085beb701d87c7c7404da.zip | |
[IA64] More Itanium PAL spec updates
Additional updates to conform with Rev 2.2 of Volume 2 of "Intel
Itanium Architecture Software Developer's Manual" (January 2006).
Add pal_bus_features_s bits 52 & 53 (page 2:347)
Add pal_vm_info_2_s field max_purges (page 2:2:451)
Add PAL_GET_HW_POLICY call (page 2:381)
Add PAL_SET_HW_POLICY call (page 2:439)
Sample output before:
---------------------------------------------------------------------
cobra:~ # cat /proc/pal/cpu0/vm_info
Physical Address Space : 50 bits
Virtual Address Space : 61 bits
Protection Key Registers(PKR) : 16
Implemented bits in PKR.key : 24
Hash Tag ID : 0x2
Size of RR.rid : 24
Supported memory attributes : WB, UC, UCE, WC, NaTPage
---------------------------------------------------------------------
Sample output after:
---------------------------------------------------------------------
cobra:~ # cat /proc/pal/cpu0/vm_info
Physical Address Space : 50 bits
Virtual Address Space : 61 bits
Protection Key Registers(PKR) : 16
Implemented bits in PKR.key : 24
Hash Tag ID : 0x2
Max Purges : 1
Size of RR.rid : 24
Supported memory attributes : WB, UC, UCE, WC, NaTPage
---------------------------------------------------------------------
Signed-off-by: Russ Anderson (rja@sgi.com)
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/lib')
0 files changed, 0 insertions, 0 deletions