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| author | H. Peter Anvin <hpa@linux.intel.com> | 2009-01-22 00:04:32 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-01-22 09:24:02 +0100 |
| commit | 066941bd4eeb159307a5d7d795100d0887c00442 (patch) | |
| tree | 2bd4dfc033f72cbe0b3532140f54df1869dd6180 /arch/ia64/xen/machvec.c | |
| parent | x86: add MSR_IA32_MISC_ENABLE bits to <asm/msr-index.h> (diff) | |
| download | linux-066941bd4eeb159307a5d7d795100d0887c00442.tar.xz linux-066941bd4eeb159307a5d7d795100d0887c00442.zip | |
x86: unmask CPUID levels on Intel CPUs
Impact: Fixes crashes with misconfigured BIOSes on XSAVE hardware
Avuton Olrich reported early boot crashes with v2.6.28 and
bisected it down to dc1e35c6e95e8923cf1d3510438b63c600fee1e2
("x86, xsave: enable xsave/xrstor on cpus with xsave support").
If the CPUID limit bit in MSR_IA32_MISC_ENABLE is set, clear it to
make all CPUID information available. This is required for some
features to work, in particular XSAVE.
Reported-and-bisected-by: Avuton Olrich <avuton@gmail.com>
Tested-by: Avuton Olrich <avuton@gmail.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/ia64/xen/machvec.c')
0 files changed, 0 insertions, 0 deletions