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| author | Huacai Chen <chenhuacai@loongson.cn> | 2024-07-20 16:41:06 +0200 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2024-07-20 16:41:06 +0200 |
| commit | f60d251b27f6599b3407950924ac9b2c7a94b714 (patch) | |
| tree | b0211b7915b34153e1933974c88b06e5fbd94000 /arch/loongarch/include/asm | |
| parent | LoongArch: Add writecombine support for DMW-based ioremap() (diff) | |
| download | linux-f60d251b27f6599b3407950924ac9b2c7a94b714.tar.xz linux-f60d251b27f6599b3407950924ac9b2c7a94b714.zip | |
LoongArch: Add architectural preparation for CPUFreq
Add architectural preparation for CPUFreq driver, including: Kconfig,
register definition and platform device registration.
Some of LoongArch processors support DVFS, their IOCSR.FEATURES has
IOCSRF_FREQSCALE set. And they has a micro-core in the package called
SMC (System Management Controller) to scale frequency, voltage, etc.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/include/asm')
| -rw-r--r-- | arch/loongarch/include/asm/loongarch.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h index c430df595376..1501f0f8b06e 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -1061,11 +1061,14 @@ #define LOONGARCH_IOCSR_NODECNT 0x408 #define LOONGARCH_IOCSR_MISC_FUNC 0x420 +#define IOCSR_MISC_FUNC_SOFT_INT BIT_ULL(10) #define IOCSR_MISC_FUNC_TIMER_RESET BIT_ULL(21) #define IOCSR_MISC_FUNC_EXT_IOI_EN BIT_ULL(48) #define LOONGARCH_IOCSR_CPUTEMP 0x428 +#define LOONGARCH_IOCSR_SMCMBX 0x51c + /* PerCore CSR, only accessible by local cores */ #define LOONGARCH_IOCSR_IPI_STATUS 0x1000 #define LOONGARCH_IOCSR_IPI_EN 0x1004 |