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authorGreg Ungerer <gerg@uclinux.org>2010-11-09 01:12:29 +0100
committerGreg Ungerer <gerg@uclinux.org>2011-01-05 06:19:18 +0100
commita12cf0a8c6e2763ac865aa31f296557e07432b8a (patch)
tree5b44bfe7aca132e1a3f0cd2bd7bbe2291b56a663 /arch/m68k/include/asm/m5206sim.h
parentm68knommu: remove empty __iounmap() it is no used (diff)
downloadlinux-a12cf0a8c6e2763ac865aa31f296557e07432b8a.tar.xz
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m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache controller unit. Create a set of bit flag definitions for the supporting registers. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m5206sim.h')
-rw-r--r--arch/m68k/include/asm/m5206sim.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index aa7ee48d5059..561b03b5ddf8 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -15,6 +15,8 @@
#define CPU_NAME "COLDFIRE(m5206)"
#define CPU_INSTR_PER_JIFFY 3
+#include <asm/m52xxacr.h>
+
/*
* Define the 5206 SIM register set addresses.
*/