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| author | Peter Turczak <peter@turczak.de> | 2011-08-09 06:11:19 +0200 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-10-18 06:22:25 +0200 |
| commit | 89127ed381fb244aa51c1a74ed695a1f3578ef7d (patch) | |
| tree | 7c0f331b438cb1f56b73bd18e39766274d43cbe5 /arch/m68k/include/asm/m520xsim.h | |
| parent | m68k: fix memcpy to unmatched/unaligned source and dest on 68000 (diff) | |
| download | linux-89127ed381fb244aa51c1a74ed695a1f3578ef7d.tar.xz linux-89127ed381fb244aa51c1a74ed695a1f3578ef7d.zip | |
m68knommu: fix problems with SPI/GPIO on ColdFire 520x
The problem has its root in the calculation of the set-port offsets (macro
MCFGPIO_SETR() in arch/m68k/include/asm/gpio.h), this assumes that all ports
have the same offset from the base port address (MCFGPIO_SETR) which is
defined in mcf520xsim.h as an alias of MCFGIO_PSETR_BUSCTL. Because the BUSCTL
and BE port do not have a set-register (see MCF5208 Reference Manual Page
13-10, Table 13-3) the offset calculations went wrong.
Because the BE and BUSCTL port do not seem useful in these parts, as they
lack a set register, I removed them and adapted the gpio chip bases which
are also used for the offset-calculations. Now both setting and resetting
the chip selects works as expected from userland and from the kernelspace.
Signed-off-by: Peter Turczak <peter@turczak.de>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m520xsim.h')
| -rw-r--r-- | arch/m68k/include/asm/m520xsim.h | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index b6bf2c518bac..eda62de7e607 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -90,15 +90,13 @@ #define MCFGPIO_PDDR_FECH 0xFC0A4013 #define MCFGPIO_PDDR_FECL 0xFC0A4014 -#define MCFGPIO_PPDSDR_BUSCTL 0xFC0A401A -#define MCFGPIO_PPDSDR_BE 0xFC0A401B -#define MCFGPIO_PPDSDR_CS 0xFC0A401C -#define MCFGPIO_PPDSDR_FECI2C 0xFC0A401D -#define MCFGPIO_PPDSDR_QSPI 0xFC0A401E -#define MCFGPIO_PPDSDR_TIMER 0xFC0A401F -#define MCFGPIO_PPDSDR_UART 0xFC0A4021 -#define MCFGPIO_PPDSDR_FECH 0xFC0A4021 -#define MCFGPIO_PPDSDR_FECL 0xFC0A4022 +#define MCFGPIO_PPDSDR_CS 0xFC0A401A +#define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B +#define MCFGPIO_PPDSDR_QSPI 0xFC0A401C +#define MCFGPIO_PPDSDR_TIMER 0xFC0A401D +#define MCFGPIO_PPDSDR_UART 0xFC0A401E +#define MCFGPIO_PPDSDR_FECH 0xFC0A401F +#define MCFGPIO_PPDSDR_FECL 0xFC0A4020 #define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 #define MCFGPIO_PCLRR_BE 0xFC0A4025 @@ -113,11 +111,11 @@ /* * Generic GPIO support */ -#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL -#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL -#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL -#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL -#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL +#define MCFGPIO_PODR MCFGPIO_PODR_CS +#define MCFGPIO_PDDR MCFGPIO_PDDR_CS +#define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS +#define MCFGPIO_SETR MCFGPIO_PPDSDR_CS +#define MCFGPIO_CLRR MCFGPIO_PCLRR_CS #define MCFGPIO_PIN_MAX 80 #define MCFGPIO_IRQ_MAX 8 |