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| author | Angelo Dureghello <angelo@kernel-space.org> | 2021-07-02 11:48:39 +0200 |
|---|---|---|
| committer | Greg Ungerer <gerg@linux-m68k.org> | 2021-08-23 00:40:04 +0200 |
| commit | 35a9f9363a89aa964c85b769c434a42b8b0f4b0d (patch) | |
| tree | 072a64529ce802180a18162ffc2fc0a984f74cff /arch/m68k/include/asm/m5441xsim.h | |
| parent | m68k: stmark2: update board setup (diff) | |
| download | linux-35a9f9363a89aa964c85b769c434a42b8b0f4b0d.tar.xz linux-35a9f9363a89aa964c85b769c434a42b8b0f4b0d.zip | |
m68k: m5441x: add flexcan support
Add flexcan support.
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
Made the flexcan resource inclusion conditional based on the enablement
of the flexcan driver. This commit is no longer dependant on the
presence of the updated driver in mainline.
Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
Diffstat (limited to 'arch/m68k/include/asm/m5441xsim.h')
| -rw-r--r-- | arch/m68k/include/asm/m5441xsim.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m5441xsim.h b/arch/m68k/include/asm/m5441xsim.h index e091e36d3464..f48cf63bd782 100644 --- a/arch/m68k/include/asm/m5441xsim.h +++ b/arch/m68k/include/asm/m5441xsim.h @@ -73,6 +73,12 @@ #define MCFINT0_FECENTC1 55 /* on interrupt controller 1 */ +#define MCFINT1_FLEXCAN0_IFL 0 +#define MCFINT1_FLEXCAN0_BOFF 1 +#define MCFINT1_FLEXCAN0_ERR 3 +#define MCFINT1_FLEXCAN1_IFL 4 +#define MCFINT1_FLEXCAN1_BOFF 5 +#define MCFINT1_FLEXCAN1_ERR 7 #define MCFINT1_UART4 48 #define MCFINT1_UART5 49 #define MCFINT1_UART6 50 @@ -314,4 +320,17 @@ #define MCF_IRQ_SDHC (MCFINT2_VECBASE + MCFINT2_SDHC) #define MCFSDHC_CLK (MCFSDHC_BASE + 0x2c) +/* + * Flexcan module + */ +#define MCFFLEXCAN_BASE0 0xfc020000 +#define MCFFLEXCAN_BASE1 0xfc024000 +#define MCFFLEXCAN_SIZE 0x4000 +#define MCF_IRQ_IFL0 (MCFINT1_VECBASE + MCFINT1_FLEXCAN0_IFL) +#define MCF_IRQ_BOFF0 (MCFINT1_VECBASE + MCFINT1_FLEXCAN0_BOFF) +#define MCF_IRQ_ERR0 (MCFINT1_VECBASE + MCFINT1_FLEXCAN0_ERR) +#define MCF_IRQ_IFL1 (MCFINT1_VECBASE + MCFINT1_FLEXCAN1_IFL) +#define MCF_IRQ_BOFF1 (MCFINT1_VECBASE + MCFINT1_FLEXCAN1_BOFF) +#define MCF_IRQ_ERR1 (MCFINT1_VECBASE + MCFINT1_FLEXCAN1_ERR) + #endif /* m5441xsim_h */ |