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author | Paul Mundt <lethal@linux-sh.org> | 2011-03-17 08:44:08 +0100 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2011-03-17 08:44:08 +0100 |
commit | 1d2a1959fe534279cf37aba20b08c24c20840e52 (patch) | |
tree | 67c0b9aa7fe22a44bf0b4af88947799203eb8f67 /arch/m68k/include/asm/m54xxsim.h | |
parent | sh: update sh7757lcr_defconfig (diff) | |
parent | Merge branch 'mnt_devname' of git://git.kernel.org/pub/scm/linux/kernel/git/v... (diff) | |
download | linux-1d2a1959fe534279cf37aba20b08c24c20840e52.tar.xz linux-1d2a1959fe534279cf37aba20b08c24c20840e52.zip |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into sh-latest
Diffstat (limited to 'arch/m68k/include/asm/m54xxsim.h')
-rw-r--r-- | arch/m68k/include/asm/m54xxsim.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h index 462ae5328441..1ed8bfb02772 100644 --- a/arch/m68k/include/asm/m54xxsim.h +++ b/arch/m68k/include/asm/m54xxsim.h @@ -7,6 +7,7 @@ #define CPU_NAME "COLDFIRE(m54xx)" #define CPU_INSTR_PER_JIFFY 2 +#define MCF_BUSCLK (MCF_CLK / 2) #include <asm/m54xxacr.h> @@ -15,7 +16,8 @@ /* * Interrupt Controller Registers */ -#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */ + #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ @@ -48,6 +50,16 @@ #define MCFGPIO_IRQ_VECBASE -1 /* + * EDGE Port support. + */ +#define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */ +#define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */ +#define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */ +#define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */ +#define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */ +#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */ + +/* * Some PSC related definitions */ #define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3)) |