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authorLinus Torvalds <torvalds@linux-foundation.org>2012-07-25 02:20:51 +0200
committerLinus Torvalds <torvalds@linux-foundation.org>2012-07-25 02:20:51 +0200
commit2c05b2c838e7adaabb7265ad5d5b632315c20821 (patch)
treecb29c9de665f216825a7932afb7c6329ab9ae158 /arch/m68k/include/asm/mcfclk.h
parentMerge branch 'next' of git://git.infradead.org/users/vkoul/slave-dma (diff)
parentm68k: allow PCI bus to be enabled for ColdFire m54xx CPUs (diff)
downloadlinux-2c05b2c838e7adaabb7265ad5d5b632315c20821.tar.xz
linux-2c05b2c838e7adaabb7265ad5d5b632315c20821.zip
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
Pull m68knommu arch update from Greg Ungerer: "Quite a varied set of changes this time. - A little more merge cleanup, this time the assembler entry code. - New sub-architecture support for the ColdFire 5251/5253 and 5441x CPU families. - Specific clk support code for the ColdFire 520x and 532x CPU familes. - Refactoring of the ColdFire GPIO support. - PCI bus support for some ColdFire CPUS that have PCI hardware (54xx family). This showed up a few problems with ColdFire cache, allocating coherent memory and bi-directional DMA support. Fixes for those too." * 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (21 commits) m68k: allow PCI bus to be enabled for ColdFire m54xx CPUs m68k: add PCI bus code support for the ColdFire M54xx SoC family m68k: add IO access definitions to support PCI on ColdFire platforms m68k: add PCI bus support definitions for the ColdFire M54xx SoC family m68k: common PCI support definitions and code m68k: add support for DMA_BIDIRECTIONAL in dma support functions m68k: fix ColdFire clear cache operation m68k: use simpler dma_alloc_coherent() for ColdFire CPUs m68knommu: platform support for 8390 based ethernet used on some boards m68knommu: Add clk definitions for m532x. m68knommu: Add clk definitions for m520x. m68knommu: Add rtc device for m5441x. m68knommu: add definitions for the third interrupt controller on devices that don't have a third interrupt controller. m68knommu: Add support for the Coldfire m5441x. m68knommu: use MCF_IRQ_PIT1 instead of MCFINT_VECBASE + MCFINT_PIT1 coldfire-qspi: Add support for the Coldfire 5251/5253. m68knommu: Add support for the Coldfire 5251/5253 m68knommu: refactor Coldfire GPIO not to require GPIOLIB, eliminate mcf_gpio_chips. m68k: merge the MMU and non-MMU versions of the entry.S code m68k: use jbsr to call functions instead of bsrl ...
Diffstat (limited to 'arch/m68k/include/asm/mcfclk.h')
-rw-r--r--arch/m68k/include/asm/mcfclk.h43
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/mcfclk.h b/arch/m68k/include/asm/mcfclk.h
new file mode 100644
index 000000000000..b676a02bb392
--- /dev/null
+++ b/arch/m68k/include/asm/mcfclk.h
@@ -0,0 +1,43 @@
+/*
+ * mcfclk.h -- coldfire specific clock structure
+ */
+
+
+#ifndef mcfclk_h
+#define mcfclk_h
+
+struct clk;
+
+#ifdef MCFPM_PPMCR0
+struct clk_ops {
+ void (*enable)(struct clk *);
+ void (*disable)(struct clk *);
+};
+
+struct clk {
+ const char *name;
+ struct clk_ops *clk_ops;
+ unsigned long rate;
+ unsigned long enabled;
+ u8 slot;
+};
+
+extern struct clk *mcf_clks[];
+extern struct clk_ops clk_ops0;
+#ifdef MCFPM_PPMCR1
+extern struct clk_ops clk_ops1;
+#endif /* MCFPM_PPMCR1 */
+
+#define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
+static struct clk __clk_##clk_bank##_##clk_slot = { \
+ .name = clk_name, \
+ .clk_ops = &clk_ops##clk_bank, \
+ .rate = clk_rate, \
+ .slot = clk_slot, \
+}
+
+void __clk_init_enabled(struct clk *);
+void __clk_init_disabled(struct clk *);
+#endif /* MCFPM_PPMCR0 */
+
+#endif /* mcfclk_h */