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| author | Finn Thain <fthain@telegraphics.com.au> | 2014-01-12 14:56:38 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert@linux-m68k.org> | 2014-01-19 11:53:22 +0100 |
| commit | 56931d73697c99ecf7aba6ae86c94d3a2d15d596 (patch) | |
| tree | 9b23e4520d20e07cdab407f790c1af96735cd33e /arch/m68k/kernel | |
| parent | m68k/irq - Use polled IRQ flag for MFP timer cascaded interrupts (diff) | |
| download | linux-56931d73697c99ecf7aba6ae86c94d3a2d15d596.tar.xz linux-56931d73697c99ecf7aba6ae86c94d3a2d15d596.zip | |
m68k/mac: Make SCC reset work more reliably
For SCC initialization we cannot assume that the control register is in
the correct state to accept a register pointer. So first read from the
control register in order to "sync" up.
Signed-off-by: Finn Thain <fthain@telegraphics.com.au>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Diffstat (limited to 'arch/m68k/kernel')
| -rw-r--r-- | arch/m68k/kernel/head.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/m68k/kernel/head.S b/arch/m68k/kernel/head.S index 7d7913f5dce3..4c99bab7e664 100644 --- a/arch/m68k/kernel/head.S +++ b/arch/m68k/kernel/head.S @@ -2915,7 +2915,9 @@ func_start serial_init,%d0/%d1/%a0/%a1 #if defined(MAC_USE_SCC_A) || defined(MAC_USE_SCC_B) movel %pc@(L(mac_sccbase)),%a0 - /* Reset SCC device */ + /* Reset SCC register pointer */ + moveb %a0@(mac_scc_cha_a_ctrl_offset),%d0 + /* Reset SCC device: write register pointer then register value */ moveb #9,%a0@(mac_scc_cha_a_ctrl_offset) moveb #0xc0,%a0@(mac_scc_cha_a_ctrl_offset) /* Wait for 5 PCLK cycles, which is about 68 CPU cycles */ |