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| author | Greg Ungerer <gerg@uclinux.org> | 2010-11-09 04:35:55 +0100 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-01-05 06:19:18 +0100 |
| commit | 8ce877a8eb8293b5b2c07f259d694026b0f519e4 (patch) | |
| tree | d478523ee8bec4ecc638c9f9a35816fc12aaa37f /arch/m68knommu/platform/coldfire | |
| parent | m68knommu: move inclusion of ColdFire v4 cache registers (diff) | |
| download | linux-8ce877a8eb8293b5b2c07f259d694026b0f519e4.tar.xz linux-8ce877a8eb8293b5b2c07f259d694026b0f519e4.zip | |
m68knommu: clean up ColdFire cache control code
The cache control code for the ColdFire CPU's is a big ugly mess
of "#ifdef"ery liberally coated with bit constants. Clean it up.
The cache controllers in the various ColdFire parts are actually quite
similar. Just differing in some bit flags and options supported. Using
the header defines now in place it is pretty easy to factor out the
small differences and use common setup and flush/invalidate code.
I have preserved the cache setups as they where in the old code
(except where obviously wrong - like in the case of the 5249). Following
from this it should be easy now to extend the possible setups used on
the CACHE controllers that support split cacheing or copy-back or
write through options.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu/platform/coldfire')
| -rw-r--r-- | arch/m68knommu/platform/coldfire/head.S | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S index 0b2d7c7adf79..d5977909ae5f 100644 --- a/arch/m68knommu/platform/coldfire/head.S +++ b/arch/m68knommu/platform/coldfire/head.S @@ -3,7 +3,7 @@ /* * head.S -- common startup code for ColdFire CPUs. * - * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>. + * (C) Copyright 1999-2010, Greg Ungerer <gerg@snapgear.com>. */ /*****************************************************************************/ @@ -13,7 +13,6 @@ #include <linux/init.h> #include <asm/asm-offsets.h> #include <asm/coldfire.h> -#include <asm/mcfcache.h> #include <asm/mcfsim.h> #include <asm/thread_info.h> @@ -173,10 +172,27 @@ _start: /* * Now that we know what the memory is, lets enable cache - * and get things moving. This is Coldfire CPU specific. + * and get things moving. This is Coldfire CPU specific. Not + * all version cores have identical cache register setup. But + * it is very similar. Define the exact settings in the headers + * then the code here is the same for all. */ - CACHE_ENABLE /* enable CPU cache */ - + movel #CACHE_INIT,%d0 /* invalidate whole cache */ + movec %d0,%CACR + nop + movel #ACR0_MODE,%d0 /* set RAM region for caching */ + movec %d0,%ACR0 + movel #ACR1_MODE,%d0 /* anything else to cache? */ + movec %d0,%ACR1 +#ifdef ACR2_MODE + movel #ACR2_MODE,%d0 + movec %d0,%ACR2 + movel #ACR3_MODE,%d0 + movec %d0,%ACR3 +#endif + movel #CACHE_MODE,%d0 /* enable cache */ + movec %d0,%CACR + nop #ifdef CONFIG_ROMFS_FS /* |