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authorSteven J. Hill <Steven.Hill@imgtec.com>2013-06-27 17:27:59 +0200
committerRalf Baechle <ralf@linux-mips.org>2013-07-01 15:10:59 +0200
commit1535ac096d26538888d00881f5026cbc8b6dc20d (patch)
tree67b50a0a5982fc11be0d6b54db5b45d79dc217c8 /arch/mips/Kconfig
parentMIPS: BCM63xx: Enable second core SMP on BCM6328 if available (diff)
downloadlinux-1535ac096d26538888d00881f5026cbc8b6dc20d.tar.xz
linux-1535ac096d26538888d00881f5026cbc8b6dc20d.zip
MIPS: SEAD3: Disable L2 cache on SEAD-3.
The cores used on the SEAD-3 platform do not have L2 caches, so this option should not be turned on. Originally fixed on public 'linux-mti-3.8' release branch. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5559/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to '')
-rw-r--r--arch/mips/Kconfig1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3a3e54cc7703..567c45b33651 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -342,7 +342,6 @@ config MIPS_SEAD3
select DMA_NONCOHERENT
select IRQ_CPU
select IRQ_GIC
- select MIPS_CPU_SCACHE
select MIPS_MSC
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2