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| author | Ben Hutchings <ben@decadent.org.uk> | 2015-05-25 21:27:29 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-06-21 21:54:19 +0200 |
| commit | df115f3ee9ea703e1209392cd08f8d6783244721 (patch) | |
| tree | dca3ae5352163462545c5436cfb3bf7105ce20b8 /arch/mips/Kconfig | |
| parent | MIPS: BMIPS: Accept UHI interface for passing a dtb (diff) | |
| download | linux-df115f3ee9ea703e1209392cd08f8d6783244721.tar.xz linux-df115f3ee9ea703e1209392cd08f8d6783244721.zip | |
MIPS: Octeon: Set OHCI and EHCI MMIO byte order to match CPU
The Octeon OHCI is now supported by the ohci-platform driver, and
USB_OCTEON_OHCI is marked as deprecated. However, it is currently
still necessary to enable it in order to select
USB_OHCI_BIG_ENDIAN_MMIO. Make CPU_CAVIUM_OCTEON select that as well,
so that USB_OCTEON_OHCI is really obsolete.
The old ohci-octeon and ehci-octeon drivers also only enabled big-endian
MMIO in case the CPU was big-endian. Make the selections of
USB_EHCI_BIG_ENDIAN_MMIO and USB_OHCI_BIG_ENDIAN_MMIO conditional, to
match this.
Fixes: 2193dda5eec6 ("USB: host: Remove ehci-octeon and ohci-octeon drivers")
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: linux-mips@linux-mips.org
Cc: David Daney <david.daney@cavium.com>
Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
Cc: Paul Martin <paul.martin@codethink.co.uk>
Patchwork: https://patchwork.linux-mips.org/patch/10178/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/Kconfig')
| -rw-r--r-- | arch/mips/Kconfig | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a2ee09c8056f..5e8ba716e441 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1574,7 +1574,8 @@ config CPU_CAVIUM_OCTEON select WEAK_ORDERING select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES - select USB_EHCI_BIG_ENDIAN_MMIO + select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN + select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN select MIPS_L1_CACHE_SHIFT_7 help The Cavium Octeon processor is a highly integrated chip containing |