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| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2023-02-21 14:16:57 +0100 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2023-03-14 17:06:16 +0100 |
| commit | 162e134aedcacc9ab9d5648349ceb5409f9ec880 (patch) | |
| tree | 8a5accfa6b37215a60edca63e98fc45f0c449c00 /arch/mips/Kconfig | |
| parent | MIPS: Loongson64: smp: Correct nudge_writes usage (diff) | |
| download | linux-162e134aedcacc9ab9d5648349ceb5409f9ec880.tar.xz linux-162e134aedcacc9ab9d5648349ceb5409f9ec880.zip | |
MIPS: Loongson64: Remove CPU_HAS_WB
Q: Do we have really have write buffer
A: Yes, on newer Loongson processors there is a "store fill buffer"
that will collect *cached* writes, on all Loongson processors
AXI crossbar will buffer all writes.
Q: Then why do we want to remove CPU_HAS_WB?
A: Because CPU_HAS_WB introduces wbflush, which intends to flush
all write reuqests to mmio device. We won't be affected by store
fill buffer because it won't buffer uncached writes. And a regular
memory barrier is sufficient to flush crossbar write buffer.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/Kconfig')
| -rw-r--r-- | arch/mips/Kconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e2f3ca73f40d..6f275ace27be 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -490,7 +490,6 @@ config MACH_LOONGSON64 select BOARD_SCACHE select CSRC_R4K select CEVT_R4K - select CPU_HAS_WB select FORCE_PCI select ISA select I8259 |