diff options
| author | Manuel Lauss <mano@roarinelk.homelinux.net> | 2008-12-21 09:26:23 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-01-11 10:57:27 +0100 |
| commit | 0c694de12b54fa96b9555e07603f567906ce21c8 (patch) | |
| tree | c7528273c1d86069cb6e83bd2b36706f663f1eb2 /arch/mips/alchemy/Kconfig | |
| parent | MIPS: make cp0 counter clocksource/event usable as fallback. (diff) | |
| download | linux-0c694de12b54fa96b9555e07603f567906ce21c8.tar.xz linux-0c694de12b54fa96b9555e07603f567906ce21c8.zip | |
MIPS: Alchemy: RTC counter clocksource / clockevent support.
Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent
device. As a nice side effect, this also enables use of the 'wait'
instruction for runtime idle power savings.
If the counters aren't enabled/working properly, fall back on the
cp0 counter clock code.
Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy/Kconfig')
| -rw-r--r-- | arch/mips/alchemy/Kconfig | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 4397d94f327a..7f8ef13d0014 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -128,8 +128,8 @@ config SOC_AU1200 config SOC_AU1X00 bool select 64BIT_PHYS_ADDR - select CEVT_R4K - select CSRC_R4K + select CEVT_R4K_LIB + select CSRC_R4K_LIB select IRQ_CPU select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_32BIT_KERNEL |