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authorTony Luck <tony.luck@intel.com>2013-07-24 19:09:43 +0200
committerTony Luck <tony.luck@intel.com>2013-07-29 20:23:27 +0200
commit1a7f0e3c4fff449f6dd08787beb98a8e57d8cdc7 (patch)
treea92404762bded6bcbadb8c3beb5a2f43362e076e /arch/mips/alchemy
parentLinux 3.11-rc3 (diff)
downloadlinux-1a7f0e3c4fff449f6dd08787beb98a8e57d8cdc7.tar.xz
linux-1a7f0e3c4fff449f6dd08787beb98a8e57d8cdc7.zip
x86/mce: Fix mce regression from recent cleanup
In commit 33d7885b594e169256daef652e8d3527b2298e75 x86/mce: Update MCE severity condition check We simplified the rules to recognise each classification of recoverable machine check combining the instruction and data fetch rules into a single entry based on clarifications in the June 2013 SDM that all recoverable events would be reported on the unaffected processor with MCG_STATUS.EIPV=0 and MCG_STATUS.RIPV=1. Unfortunately the simplified rule has a couple of bugs. Fix them here. Acked-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
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