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authorWeijie Gao <hackpascal@gmail.com>2016-03-17 04:34:09 +0100
committerRalf Baechle <ralf@linux-mips.org>2016-04-03 12:32:09 +0200
commitc338d59d12dc93c3287160acd7e726b56dc94f43 (patch)
treef26c90d90253ebd00fac0d964b152f09a9bc2fba /arch/mips/ath79
parentdt-bindings: clock: qca,ath79-pll: fix copy-paste typos (diff)
downloadlinux-c338d59d12dc93c3287160acd7e726b56dc94f43.tar.xz
linux-c338d59d12dc93c3287160acd7e726b56dc94f43.zip
MIPS: ath79: Fix the ar724x clock calculation
According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz input clock as the REF_CLK instead of 5MHz. The correct CPU PLL calculation procedure is as follows: CPU_PLL = (FB * REF_CLK) / REF_DIV / 2. This patch is compatible with the current calculation procedure with default FB and REF_DIV values. Tested on AR7240, AR7241 and AR7242. Signed-off-by: Weijie Gao <hackpascal@gmail.com> Signed-off-by: Alban Bedel <albeu@free.fr> (Fixed the commit log message) Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12870/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ath79')
-rw-r--r--arch/mips/ath79/clock.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index eb5117ced95a..ed2846578405 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -26,7 +26,7 @@
#include "common.h"
#define AR71XX_BASE_FREQ 40000000
-#define AR724X_BASE_FREQ 5000000
+#define AR724X_BASE_FREQ 40000000
#define AR913X_BASE_FREQ 5000000
static struct clk *clks[3];
@@ -103,8 +103,8 @@ static void __init ar724x_clocks_init(void)
div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
freq = div * ref_rate;
- div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
- freq *= div;
+ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
+ freq /= div;
cpu_rate = freq;