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| author | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2018-07-31 16:38:54 +0200 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2018-07-31 19:34:08 +0200 |
| commit | 9eaf3ba5e0557eef9c3d9a64c72b9352cdc49d50 (patch) | |
| tree | b15570261018b5500c1d44aa6349ac8dd9b46056 /arch/mips/boot | |
| parent | MIPS: Loongson: Merge load addresses (diff) | |
| download | linux-9eaf3ba5e0557eef9c3d9a64c72b9352cdc49d50.tar.xz linux-9eaf3ba5e0557eef9c3d9a64c72b9352cdc49d50.zip | |
mips: dts: mscc: Add spi on Ocelot
Add support for the SPI controller
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20101/
Cc: Mark Brown <broonie@kernel.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-spi@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Allan Nielsen <allan.nielsen@microsemi.com>
Diffstat (limited to 'arch/mips/boot')
| -rw-r--r-- | arch/mips/boot/dts/mscc/ocelot.dtsi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi index afe8fc9011ea..f7eb612b46ba 100644 --- a/arch/mips/boot/dts/mscc/ocelot.dtsi +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi @@ -91,6 +91,17 @@ status = "disabled"; }; + spi: spi@101000 { + compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x101000 0x100>, <0x3c 0x18>; + interrupts = <9>; + clocks = <&ahb_clk>; + + status = "disabled"; + }; + switch@1010000 { compatible = "mscc,vsc7514-switch"; reg = <0x1010000 0x10000>, |