diff options
| author | Tejun Heo <tj@kernel.org> | 2009-08-14 07:41:02 +0200 |
|---|---|---|
| committer | Tejun Heo <tj@kernel.org> | 2009-08-14 07:45:31 +0200 |
| commit | 384be2b18a5f9475eab9ca2bdfa95cc1a04ef59c (patch) | |
| tree | 04c93f391a1b65c8bf8d7ba8643c07d26c26590a /arch/mips/cavium-octeon/smp.c | |
| parent | percpu: add dummy pcpu_lpage_remapped() for !CONFIG_SMP (diff) | |
| parent | percpu: use the right flag for get_vm_area() (diff) | |
| download | linux-384be2b18a5f9475eab9ca2bdfa95cc1a04ef59c.tar.xz linux-384be2b18a5f9475eab9ca2bdfa95cc1a04ef59c.zip | |
Merge branch 'percpu-for-linus' into percpu-for-next
Conflicts:
arch/sparc/kernel/smp_64.c
arch/x86/kernel/cpu/perf_counter.c
arch/x86/kernel/setup_percpu.c
drivers/cpufreq/cpufreq_ondemand.c
mm/percpu.c
Conflicts in core and arch percpu codes are mostly from commit
ed78e1e078dd44249f88b1dd8c76dafb39567161 which substituted many
num_possible_cpus() with nr_cpu_ids. As for-next branch has moved all
the first chunk allocators into mm/percpu.c, the changes are moved
from arch code to mm/percpu.c.
Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'arch/mips/cavium-octeon/smp.c')
| -rw-r--r-- | arch/mips/cavium-octeon/smp.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 0b891a9c6253..32d51a31dc48 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -194,11 +194,11 @@ static void octeon_init_secondary(void) void octeon_prepare_cpus(unsigned int max_cpus) { cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff); - if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_SHARED, + if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED, "mailbox0", mailbox_interrupt)) { panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n"); } - if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_SHARED, + if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_DISABLED, "mailbox1", mailbox_interrupt)) { panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n"); } |