diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2013-07-02 17:19:04 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-07-12 18:11:43 +0200 |
| commit | 6ac5310e649df5fcd240d764503bf16a1317ea39 (patch) | |
| tree | 286700815b3f30dc13cc3b2d9980b0244b244d33 /arch/mips/cavium-octeon | |
| parent | MIPS: Kconfig: Add missing MODULES dependency to VPE_LOADER (diff) | |
| parent | MIPS: tlbex: Fix size of area to be flushed. (diff) | |
| download | linux-6ac5310e649df5fcd240d764503bf16a1317ea39.tar.xz linux-6ac5310e649df5fcd240d764503bf16a1317ea39.zip | |
Merge branch '3.10-fixes' into mips-for-linux-next
This that should have been fixed but weren't, way to much, intrusive
and late.
Diffstat (limited to 'arch/mips/cavium-octeon')
| -rw-r--r-- | arch/mips/cavium-octeon/Makefile | 3 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/setup.c | 5 |
2 files changed, 5 insertions, 3 deletions
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index b703583779fb..4e952043c922 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -13,10 +13,11 @@ CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o -obj-y += dma-octeon.o flash_setup.o +obj-y += dma-octeon.o obj-y += octeon-memcpy.o obj-y += executive/ +obj-$(CONFIG_MTD) += flash_setup.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 0acc8ef86907..48b08eb9d9e4 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -7,6 +7,7 @@ * Copyright (C) 2008, 2009 Wind River Systems * written by Ralf Baechle <ralf@linux-mips.org> */ +#include <linux/compiler.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/console.h> @@ -694,7 +695,7 @@ void __init prom_init(void) if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { pr_info("Skipping L2 locking due to reduced L2 cache size\n"); } else { - uint32_t ebase = read_c0_ebase() & 0x3ffff000; + uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000; #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB /* TLB refill */ cvmx_l2c_lock_mem_region(ebase, 0x100); @@ -978,7 +979,7 @@ void __init plat_mem_setup(void) cvmx_bootmem_unlock(); /* Add the memory region for the kernel. */ kernel_start = (unsigned long) _text; - kernel_size = ALIGN(_end - _text, 0x100000); + kernel_size = _end - _text; /* Adjust for physical offset. */ kernel_start &= ~0xffffffff80000000ULL; |