diff options
| author | Aaro Koskinen <aaro.koskinen@iki.fi> | 2018-12-04 21:12:16 +0100 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2018-12-05 00:48:57 +0100 |
| commit | 8b5c4eb17192d1dc8d2bb97432ca70aeeb7f634b (patch) | |
| tree | df555ce6e626dcd9533b4563ea8b9c222ded2b87 /arch/mips/cavium-octeon | |
| parent | MIPS: OCTEON: enable all OCTEON drivers in defconfig (diff) | |
| download | linux-8b5c4eb17192d1dc8d2bb97432ca70aeeb7f634b.tar.xz linux-8b5c4eb17192d1dc8d2bb97432ca70aeeb7f634b.zip | |
MIPS: OCTEON: octeon-usb: use common gpio_bit definition
cvmx_gpio_bit_cfgx bitfields are indentical on cn70xx and cn73xx,
and also match the default definition. So use that instead.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Diffstat (limited to 'arch/mips/cavium-octeon')
| -rw-r--r-- | arch/mips/cavium-octeon/octeon-usb.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c index bfdfaf32d2c4..1f730ded5224 100644 --- a/arch/mips/cavium-octeon/octeon-usb.c +++ b/arch/mips/cavium-octeon/octeon-usb.c @@ -253,17 +253,17 @@ static int dwc3_octeon_config_power(struct device *dev, u64 base) && gpio <= 31) { gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); gpio_bit.s.tx_oe = 1; - gpio_bit.cn73xx.output_sel = (index == 0 ? 0x14 : 0x15); + gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15); cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); } else if (gpio <= 15) { gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); gpio_bit.s.tx_oe = 1; - gpio_bit.cn70xx.output_sel = (index == 0 ? 0x14 : 0x19); + gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19); cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); } else { gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio)); gpio_bit.s.tx_oe = 1; - gpio_bit.cn70xx.output_sel = (index == 0 ? 0x14 : 0x19); + gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19); cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64); } |