Merge tag 'mips_6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Thomas Bogendoerfer:

 - add support for TP-Link HC220 G5 v1

 - add support for Wifi/Bluetooth on CI20

 - rework Ralink clock and reset handling

 - cleanups and fixes

* tag 'mips_6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (58 commits)
  MIPS: Loongson64: DTS: Add RTC support to Loongson-2K1000
  MIPS: Loongson64: DTS: Add RTC support to LS7A PCH
  MIPS: OCTEON: octeon-usb: cleanup divider calculation
  MIPS: OCTEON: octeon-usb: introduce dwc3_octeon_{read,write}q
  MIPS: OCTEON: octeon-usb: move gpio config to separate function
  MIPS: OCTEON: octeon-usb: use bitfields for shim register
  MIPS: OCTEON: octeon-usb: use bitfields for host config register
  MIPS: OCTEON: octeon-usb: use bitfields for control register
  MIPS: OCTEON: octeon-usb: add all register offsets
  mips: ralink: match all supported system controller compatible strings
  MIPS: dec: prom: Address -Warray-bounds warning
  MIPS: DTS: CI20: Raise VDDCORE voltage to 1.125 volts
  clk: ralink: mtmips: Fix uninitialized use of ret in mtmips_register_{fixed,factor}_clocks()
  mips: ralink: introduce commonly used remap node function
  mips: pci-mt7620: use dev_info() to log PCIe device detection result
  mips: pci-mt7620: do not print NFTS register value as error log
  MAINTAINERS: add Mediatek MTMIPS Clock maintainer
  mips: ralink: get cpu rate from new driver code
  mips: ralink: remove reset related code
  mips: ralink: mt7620: remove clock related code
  ...

1 files changed, 316 insertions, 313 deletions

diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c
index 28677c615175..2add435ad038 100644
--- a/arch/mips/cavium-octeon/octeon-usb.c
+++ b/arch/mips/cavium-octeon/octeon-usb.c
@@ -8,232 +8,255 @@
  * for more details.
  */
 
-#include <linux/module.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
 #include <linux/device.h>
-#include <linux/mutex.h>
 #include <linux/delay.h>
-#include <linux/of_platform.h>
 #include <linux/io.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_platform.h>
 
-#include <asm/octeon/octeon.h>
+/*
+ * USB Control Register
+ */
+#define USBDRD_UCTL_CTL				0x00
+/* BIST fast-clear mode select. A BIST run with this bit set
+ * clears all entries in USBH RAMs to 0x0.
+ */
+# define USBDRD_UCTL_CTL_CLEAR_BIST		BIT(63)
+/* 1 = Start BIST and cleared by hardware */
+# define USBDRD_UCTL_CTL_START_BIST		BIT(62)
+/* Reference clock select for SuperSpeed and HighSpeed PLLs:
+ *	0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
+ *	0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
+ *	0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
+ *	      HighSpeed PLL uses PLL_REF_CLK for reference clck
+ *	0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
+ *	      HighSpeed PLL uses PLL_REF_CLK for reference clck
+ */
+# define USBDRD_UCTL_CTL_REF_CLK_SEL		GENMASK(61, 60)
+/* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
+# define USBDRD_UCTL_CTL_SSC_EN			BIT(59)
+/* Spread-spectrum clock modulation range:
+ *	0x0 = -4980 ppm downspread
+ *	0x1 = -4492 ppm downspread
+ *	0x2 = -4003 ppm downspread
+ *	0x3 - 0x7 = Reserved
+ */
+# define USBDRD_UCTL_CTL_SSC_RANGE		GENMASK(58, 56)
+/* Enable non-standard oscillator frequencies:
+ *	[55:53] = modules -1
+ *	[52:47] = 2's complement push amount, 0 = Feature disabled
+ */
+# define USBDRD_UCTL_CTL_SSC_REF_CLK_SEL	GENMASK(55, 47)
+/* Reference clock multiplier for non-standard frequencies:
+ *	0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
+ *	0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
+ *	0x32 =  50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
+ *	Other Values = Reserved
+ */
+# define USBDRD_UCTL_CTL_MPLL_MULTIPLIER	GENMASK(46, 40)
+/* Enable reference clock to prescaler for SuperSpeed functionality.
+ * Should always be set to "1"
+ */
+# define USBDRD_UCTL_CTL_REF_SSP_EN		BIT(39)
+/* Divide the reference clock by 2 before entering the
+ * REF_CLK_FSEL divider:
+ *	If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal
+ *	If REF_CLK_SEL = 0x2 or 0x3, then:
+ *		0x1 = DLMC_REF_CLK* is 125MHz
+ *		0x0 = DLMC_REF_CLK* is another supported frequency
+ */
+# define USBDRD_UCTL_CTL_REF_CLK_DIV2		BIT(38)
+/* Select reference clock freqnuency for both PLL blocks:
+ *	0x27 = REF_CLK_SEL is 0x0 or 0x1
+ *	0x07 = REF_CLK_SEL is 0x2 or 0x3
+ */
+# define USBDRD_UCTL_CTL_REF_CLK_FSEL		GENMASK(37, 32)
+/* Controller clock enable. */
+# define USBDRD_UCTL_CTL_H_CLK_EN		BIT(30)
+/* Select bypass input to controller clock divider:
+ *	0x0 = Use divided coprocessor clock from H_CLKDIV
+ *	0x1 = Use clock from GPIO pins
+ */
+# define USBDRD_UCTL_CTL_H_CLK_BYP_SEL		BIT(29)
+/* Reset controller clock divider. */
+# define USBDRD_UCTL_CTL_H_CLKDIV_RST		BIT(28)
+/* Clock divider select:
+ *	0x0 = divide by 1
+ *	0x1 = divide by 2
+ *	0x2 = divide by 4
+ *	0x3 = divide by 6
+ *	0x4 = divide by 8
+ *	0x5 = divide by 16
+ *	0x6 = divide by 24
+ *	0x7 = divide by 32
+ */
+# define USBDRD_UCTL_CTL_H_CLKDIV_SEL		GENMASK(26, 24)
+/* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */
+# define USBDRD_UCTL_CTL_USB3_PORT_PERM_ATTACH	BIT(21)
+/* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */
+# define USBDRD_UCTL_CTL_USB2_PORT_PERM_ATTACH	BIT(20)
+/* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
+# define USBDRD_UCTL_CTL_USB3_PORT_DISABLE	BIT(18)
+/* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */
+# define USBDRD_UCTL_CTL_USB2_PORT_DISABLE	BIT(16)
+/* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
+# define USBDRD_UCTL_CTL_SS_POWER_EN		BIT(14)
+/* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */
+# define USBDRD_UCTL_CTL_HS_POWER_EN		BIT(12)
+/* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
+# define USBDRD_UCTL_CTL_CSCLK_EN		BIT(4)
+/* Controller mode: 0x0 = Host, 0x1 = Device */
+# define USBDRD_UCTL_CTL_DRD_MODE		BIT(3)
+/* PHY reset */
+# define USBDRD_UCTL_CTL_UPHY_RST		BIT(2)
+/* Software reset UAHC */
+# define USBDRD_UCTL_CTL_UAHC_RST		BIT(1)
+/* Software resets UCTL */
+# define USBDRD_UCTL_CTL_UCTL_RST		BIT(0)
+
+#define USBDRD_UCTL_BIST_STATUS			0x08
+#define USBDRD_UCTL_SPARE0			0x10
+#define USBDRD_UCTL_INTSTAT			0x30
+#define USBDRD_UCTL_PORT_CFG_HS(port)		(0x40 + (0x20 * port))
+#define USBDRD_UCTL_PORT_CFG_SS(port)		(0x48 + (0x20 * port))
+#define USBDRD_UCTL_PORT_CR_DBG_CFG(port)	(0x50 + (0x20 * port))
+#define USBDRD_UCTL_PORT_CR_DBG_STATUS(port)	(0x58 + (0x20 * port))
 
-/* USB Control Register */
-union cvm_usbdrd_uctl_ctl {
-	uint64_t u64;
-	struct cvm_usbdrd_uctl_ctl_s {
-	/* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */
-	__BITFIELD_FIELD(uint64_t clear_bist:1,
-	/* 1 = Start BIST and cleared by hardware */
-	__BITFIELD_FIELD(uint64_t start_bist:1,
-	/* Reference clock select for SuperSpeed and HighSpeed PLLs:
-	 *	0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
-	 *	0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
-	 *	0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
-	 *	      HighSpeed PLL uses PLL_REF_CLK for reference clck
-	 *	0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
-	 *	      HighSpeed PLL uses PLL_REF_CLK for reference clck
-	 */
-	__BITFIELD_FIELD(uint64_t ref_clk_sel:2,
-	/* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
-	__BITFIELD_FIELD(uint64_t ssc_en:1,
-	/* Spread-spectrum clock modulation range:
-	 *	0x0 = -4980 ppm downspread
-	 *	0x1 = -4492 ppm downspread
-	 *	0x2 = -4003 ppm downspread
-	 *	0x3 - 0x7 = Reserved
-	 */
-	__BITFIELD_FIELD(uint64_t ssc_range:3,
-	/* Enable non-standard oscillator frequencies:
-	 *	[55:53] = modules -1
-	 *	[52:47] = 2's complement push amount, 0 = Feature disabled
-	 */
-	__BITFIELD_FIELD(uint64_t ssc_ref_clk_sel:9,
-	/* Reference clock multiplier for non-standard frequencies:
-	 *	0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
-	 *	0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
-	 *	0x32 =  50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
-	 *	Other Values = Reserved
-	 */
-	__BITFIELD_FIELD(uint64_t mpll_multiplier:7,
-	/* Enable reference clock to prescaler for SuperSpeed functionality.
-	 * Should always be set to "1"
-	 */
-	__BITFIELD_FIELD(uint64_t ref_ssp_en:1,
-	/* Divide the reference clock by 2 before entering the
-	 * REF_CLK_FSEL divider:
-	 *	If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal
-	 *	If REF_CLK_SEL = 0x2 or 0x3, then:
-	 *		0x1 = DLMC_REF_CLK* is 125MHz
-	 *		0x0 = DLMC_REF_CLK* is another supported frequency
-	 */
-	__BITFIELD_FIELD(uint64_t ref_clk_div2:1,
-	/* Select reference clock freqnuency for both PLL blocks:
-	 *	0x27 = REF_CLK_SEL is 0x0 or 0x1
-	 *	0x07 = REF_CLK_SEL is 0x2 or 0x3
-	 */
-	__BITFIELD_FIELD(uint64_t ref_clk_fsel:6,
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_31_31:1,
-	/* Controller clock enable. */
-	__BITFIELD_FIELD(uint64_t h_clk_en:1,
-	/* Select bypass input to controller clock divider:
-	 *	0x0 = Use divided coprocessor clock from H_CLKDIV
-	 *	0x1 = Use clock from GPIO pins
-	 */
-	__BITFIELD_FIELD(uint64_t h_clk_byp_sel:1,
-	/* Reset controller clock divider. */
-	__BITFIELD_FIELD(uint64_t h_clkdiv_rst:1,
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_27_27:1,
-	/* Clock divider select:
-	 *	0x0 = divide by 1
-	 *	0x1 = divide by 2
-	 *	0x2 = divide by 4
-	 *	0x3 = divide by 6
-	 *	0x4 = divide by 8
-	 *	0x5 = divide by 16
-	 *	0x6 = divide by 24
-	 *	0x7 = divide by 32
-	 */
-	__BITFIELD_FIELD(uint64_t h_clkdiv_sel:3,
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_22_23:2,
-	/* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */
-	__BITFIELD_FIELD(uint64_t usb3_port_perm_attach:1,
-	/* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */
-	__BITFIELD_FIELD(uint64_t usb2_port_perm_attach:1,
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_19_19:1,
-	/* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
-	__BITFIELD_FIELD(uint64_t usb3_port_disable:1,
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_17_17:1,
-	/* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */
-	__BITFIELD_FIELD(uint64_t usb2_port_disable:1,
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_15_15:1,
-	/* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
-	__BITFIELD_FIELD(uint64_t ss_power_en:1,
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_13_13:1,
-	/* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */
-	__BITFIELD_FIELD(uint64_t hs_power_en:1,
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_5_11:7,
-	/* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
-	__BITFIELD_FIELD(uint64_t csclk_en:1,
-	/* Controller mode: 0x0 = Host, 0x1 = Device */
-	__BITFIELD_FIELD(uint64_t drd_mode:1,
-	/* PHY reset */
-	__BITFIELD_FIELD(uint64_t uphy_rst:1,
-	/* Software reset UAHC */
-	__BITFIELD_FIELD(uint64_t uahc_rst:1,
-	/* Software resets UCTL */
-	__BITFIELD_FIELD(uint64_t uctl_rst:1,
-	;)))))))))))))))))))))))))))))))))
-	} s;
-};
-
-/* UAHC Configuration Register */
-union cvm_usbdrd_uctl_host_cfg {
-	uint64_t u64;
-	struct cvm_usbdrd_uctl_host_cfg_s {
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_60_63:4,
-	/* Indicates minimum value of all received BELT values */
-	__BITFIELD_FIELD(uint64_t host_current_belt:12,
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_38_47:10,
-	/* HS jitter adjustment */
-	__BITFIELD_FIELD(uint64_t fla:6,
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_29_31:3,
-	/* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
-	__BITFIELD_FIELD(uint64_t bme:1,
-	/* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */
-	__BITFIELD_FIELD(uint64_t oci_en:1,
-	/* Overcurrent sene selection:
-	 *	0x0 = Overcurrent indication from off-chip is active-low
-	 *	0x1 = Overcurrent indication from off-chip is active-high
-	 */
-	__BITFIELD_FIELD(uint64_t oci_active_high_en:1,
-	/* Port power control enable: 0x0 = unavailable, 0x1 = available */
-	__BITFIELD_FIELD(uint64_t ppc_en:1,
-	/* Port power control sense selection:
-	 *	0x0 = Port power to off-chip is active-low
-	 *	0x1 = Port power to off-chip is active-high
-	 */
-	__BITFIELD_FIELD(uint64_t ppc_active_high_en:1,
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_0_23:24,
-	;)))))))))))
-	} s;
-};
-
-/* UCTL Shim Features Register */
-union cvm_usbdrd_uctl_shim_cfg {
-	uint64_t u64;
-	struct cvm_usbdrd_uctl_shim_cfg_s {
-	/* Out-of-bound UAHC register access: 0 = read, 1 = write */
-	__BITFIELD_FIELD(uint64_t xs_ncb_oob_wrn:1,
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_60_62:3,
-	/* SRCID error log for out-of-bound UAHC register access:
-	 *	[59:58] = chipID
-	 *	[57] = Request source: 0 = core, 1 = NCB-device
-	 *	[56:51] = Core/NCB-device number, [56] always 0 for NCB devices
-	 *	[50:48] = SubID
-	 */
-	__BITFIELD_FIELD(uint64_t xs_ncb_oob_osrc:12,
-	/* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */
-	__BITFIELD_FIELD(uint64_t xm_bad_dma_wrn:1,
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_44_46:3,
-	/* Encoded error type for bad UAHC DMA */
-	__BITFIELD_FIELD(uint64_t xm_bad_dma_type:4,
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_13_39:27,
-	/* Select the IOI read command used by DMA accesses */
-	__BITFIELD_FIELD(uint64_t dma_read_cmd:1,
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_10_11:2,
-	/* Select endian format for DMA accesses to the L2c:
-	 *	0x0 = Little endian
-	 *`	0x1 = Big endian
-	 *	0x2 = Reserved
-	 *	0x3 = Reserved
-	 */
-	__BITFIELD_FIELD(uint64_t dma_endian_mode:2,
-	/* Reserved */
-	__BITFIELD_FIELD(uint64_t reserved_2_7:6,
-	/* Select endian format for IOI CSR access to UAHC:
-	 *	0x0 = Little endian
-	 *`	0x1 = Big endian
-	 *	0x2 = Reserved
-	 *	0x3 = Reserved
-	 */
-	__BITFIELD_FIELD(uint64_t csr_endian_mode:2,
-	;))))))))))))
-	} s;
-};
+/*
+ * UCTL Configuration Register
+ */
+#define USBDRD_UCTL_HOST_CFG			0xe0
+/* Indicates minimum value of all received BELT values */
+# define USBDRD_UCTL_HOST_CFG_HOST_CURRENT_BELT	GENMASK(59, 48)
+/* HS jitter adjustment */
+# define USBDRD_UCTL_HOST_CFG_FLA		GENMASK(37, 32)
+/* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
+# define USBDRD_UCTL_HOST_CFG_BME		BIT(28)
+/* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */
+# define USBDRD_UCTL_HOST_OCI_EN		BIT(27)
+/* Overcurrent sene selection:
+ *	0x0 = Overcurrent indication from off-chip is active-low
+ *	0x1 = Overcurrent indication from off-chip is active-high
+ */
+# define USBDRD_UCTL_HOST_OCI_ACTIVE_HIGH_EN	BIT(26)
+/* Port power control enable: 0x0 = unavailable, 0x1 = available */
+# define USBDRD_UCTL_HOST_PPC_EN		BIT(25)
+/* Port power control sense selection:
+ *	0x0 = Port power to off-chip is active-low
+ *	0x1 = Port power to off-chip is active-high
+ */
+# define USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN	BIT(24)
+
+/*
+ * UCTL Shim Features Register
+ */
+#define USBDRD_UCTL_SHIM_CFG			0xe8
+/* Out-of-bound UAHC register access: 0 = read, 1 = write */
+# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_WRN	BIT(63)
+/* SRCID error log for out-of-bound UAHC register access:
+ *	[59:58] = chipID
+ *	[57] = Request source: 0 = core, 1 = NCB-device
+ *	[56:51] = Core/NCB-device number, [56] always 0 for NCB devices
+ *	[50:48] = SubID
+ */
+# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_OSRC	GENMASK(59, 48)
+/* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */
+# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_WRN	BIT(47)
+/* Encoded error type for bad UAHC DMA */
+# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_TYPE	GENMASK(43, 40)
+/* Select the IOI read command used by DMA accesses */
+# define USBDRD_UCTL_SHIM_CFG_DMA_READ_CMD	BIT(12)
+/* Select endian format for DMA accesses to the L2C:
+ *	0x0 = Little endian
+ *	0x1 = Big endian
+ *	0x2 = Reserved
+ *	0x3 = Reserved
+ */
+# define USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE	GENMASK(9, 8)
+/* Select endian format for IOI CSR access to UAHC:
+ *	0x0 = Little endian
+ *	0x1 = Big endian
+ *	0x2 = Reserved
+ *	0x3 = Reserved
+ */
+# define USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE	GENMASK(1, 0)
 
-#define OCTEON_H_CLKDIV_SEL		8
-#define OCTEON_MIN_H_CLK_RATE		150000000
-#define OCTEON_MAX_H_CLK_RATE		300000000
+#define USBDRD_UCTL_ECC				0xf0
+#define USBDRD_UCTL_SPARE1			0xf8
 
 static DEFINE_MUTEX(dwc3_octeon_clocks_mutex);
-static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
 
+#ifdef CONFIG_CAVIUM_OCTEON_SOC
+#include <asm/octeon/octeon.h>
+static inline uint64_t dwc3_octeon_readq(void __iomem *addr)
+{
+	return cvmx_readq_csr(addr);
+}
 
-static int dwc3_octeon_config_power(struct device *dev, u64 base)
+static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val)
+{
+	cvmx_writeq_csr(base, val);
+}
+
+static void dwc3_octeon_config_gpio(int index, int gpio)
 {
-#define UCTL_HOST_CFG	0xe0
-	union cvm_usbdrd_uctl_host_cfg uctl_host_cfg;
 	union cvmx_gpio_bit_cfgx gpio_bit;
+
+	if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
+	    OCTEON_IS_MODEL(OCTEON_CNF75XX))
+	    && gpio <= 31) {
+		gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
+		gpio_bit.s.tx_oe = 1;
+		gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15);
+		cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
+	} else if (gpio <= 15) {
+		gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
+		gpio_bit.s.tx_oe = 1;
+		gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
+		cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
+	} else {
+		gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio));
+		gpio_bit.s.tx_oe = 1;
+		gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
+		cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64);
+	}
+}
+#else
+static inline uint64_t dwc3_octeon_readq(void __iomem *addr)
+{
+	return 0;
+}
+
+static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) { }
+
+static inline void dwc3_octeon_config_gpio(int index, int gpio) { }
+#endif
+
+static int dwc3_octeon_get_divider(void)
+{
+	static const uint8_t clk_div[] = { 1, 2, 4, 6, 8, 16, 24, 32 };
+	int div = 0;
+
+	while (div < ARRAY_SIZE(clk_div)) {
+		uint64_t rate = octeon_get_io_clock_rate() / clk_div[div];
+		if (rate <= 300000000 && rate >= 150000000)
+			break;
+		div++;
+	}
+
+	return div;
+}
+
+static int dwc3_octeon_config_power(struct device *dev, void __iomem *base)
+{
 	uint32_t gpio_pwr[3];
 	int gpio, len, power_active_low;
 	struct device_node *node = dev->of_node;
-	int index = (base >> 24) & 1;
+	u64 val;
+	void __iomem *uctl_host_cfg_reg = base + USBDRD_UCTL_HOST_CFG;
 
 	if (of_find_property(node, "power", &len) != NULL) {
 		if (len == 12) {
@@ -248,51 +271,33 @@ static int dwc3_octeon_config_power(struct device *dev, u64 base)
 			dev_err(dev, "invalid power configuration\n");
 			return -EINVAL;
 		}
-		if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
-		    OCTEON_IS_MODEL(OCTEON_CNF75XX))
-		    && gpio <= 31) {
-			gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
-			gpio_bit.s.tx_oe = 1;
-			gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15);
-			cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
-		} else if (gpio <= 15) {
-			gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
-			gpio_bit.s.tx_oe = 1;
-			gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
-			cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
-		} else {
-			gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio));
-			gpio_bit.s.tx_oe = 1;
-			gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
-			cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64);
-		}
+		dwc3_octeon_config_gpio(((u64)base >> 24) & 1, gpio);
 
 		/* Enable XHCI power control and set if active high or low. */
-		uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
-		uctl_host_cfg.s.ppc_en = 1;
-		uctl_host_cfg.s.ppc_active_high_en = !power_active_low;
-		cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
+		val = dwc3_octeon_readq(uctl_host_cfg_reg);
+		val |= USBDRD_UCTL_HOST_PPC_EN;
+		if (power_active_low)
+			val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN;
+		else
+			val |= USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN;
+		dwc3_octeon_writeq(uctl_host_cfg_reg, val);
 	} else {
 		/* Disable XHCI power control and set if active high. */
-		uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
-		uctl_host_cfg.s.ppc_en = 0;
-		uctl_host_cfg.s.ppc_active_high_en = 0;
-		cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
+		val = dwc3_octeon_readq(uctl_host_cfg_reg);
+		val &= ~USBDRD_UCTL_HOST_PPC_EN;
+		val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN;
+		dwc3_octeon_writeq(uctl_host_cfg_reg, val);
 		dev_info(dev, "power control disabled\n");
 	}
 	return 0;
 }
 
-static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
+static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base)
 {
-	union cvm_usbdrd_uctl_ctl uctl_ctl;
-	int ref_clk_sel = 2;
-	u64 div;
+	int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2;
 	u32 clock_rate;
-	int mpll_mul;
-	int i;
-	u64 h_clk_rate;
-	u64 uctl_ctl_reg = base;
+	u64 val;
+	void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL;
 
 	if (dev->of_node) {
 		const char *ss_clock_type;
@@ -356,44 +361,42 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
 	/* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */
 
 	/* Step 3: Assert all resets. */
-	uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
-	uctl_ctl.s.uphy_rst = 1;
-	uctl_ctl.s.uahc_rst = 1;
-	uctl_ctl.s.uctl_rst = 1;
-	cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
+	val = dwc3_octeon_readq(uctl_ctl_reg);
+	val |= USBDRD_UCTL_CTL_UPHY_RST |
+	       USBDRD_UCTL_CTL_UAHC_RST |
+	       USBDRD_UCTL_CTL_UCTL_RST;
+	dwc3_octeon_writeq(uctl_ctl_reg, val);
 
 	/* Step 4a: Reset the clock dividers. */
-	uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
-	uctl_ctl.s.h_clkdiv_rst = 1;
-	cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
+	val = dwc3_octeon_readq(uctl_ctl_reg);
+	val |= USBDRD_UCTL_CTL_H_CLKDIV_RST;
+	dwc3_octeon_writeq(uctl_ctl_reg, val);
 
 	/* Step 4b: Select controller clock frequency. */
-	for (div = 0; div < OCTEON_H_CLKDIV_SEL; div++) {
-		h_clk_rate = octeon_get_io_clock_rate() / clk_div[div];
-		if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE &&
-				 h_clk_rate >= OCTEON_MIN_H_CLK_RATE)
-			break;
-	}
-	uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
-	uctl_ctl.s.h_clkdiv_sel = div;
-	uctl_ctl.s.h_clk_en = 1;
-	cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
-	uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
-	if ((div != uctl_ctl.s.h_clkdiv_sel) || (!uctl_ctl.s.h_clk_en)) {
+	div = dwc3_octeon_get_divider();
+	val = dwc3_octeon_readq(uctl_ctl_reg);
+	val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL;
+	val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div);
+	val |= USBDRD_UCTL_CTL_H_CLK_EN;
+	dwc3_octeon_writeq(uctl_ctl_reg, val);
+	val = dwc3_octeon_readq(uctl_ctl_reg);
+	if ((div != FIELD_GET(USBDRD_UCTL_CTL_H_CLKDIV_SEL, val)) ||
+	    (!(FIELD_GET(USBDRD_UCTL_CTL_H_CLK_EN, val)))) {
 		dev_err(dev, "dwc3 controller clock init failure.\n");
 			return -EINVAL;
 	}
 
 	/* Step 4c: Deassert the controller clock divider reset. */
-	uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
-	uctl_ctl.s.h_clkdiv_rst = 0;
-	cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
+	val &= ~USBDRD_UCTL_CTL_H_CLKDIV_RST;
+	dwc3_octeon_writeq(uctl_ctl_reg, val);
 
 	/* Step 5a: Reference clock configuration. */
-	uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
-	uctl_ctl.s.ref_clk_sel = ref_clk_sel;
-	uctl_ctl.s.ref_clk_fsel = 0x07;
-	uctl_ctl.s.ref_clk_div2 = 0;
+	val = dwc3_octeon_readq(uctl_ctl_reg);
+	val &= ~USBDRD_UCTL_CTL_REF_CLK_DIV2;
+	val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL;
+	val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel);
+
+	ref_clk_fsel = 0x07;
 	switch (clock_rate) {
 	default:
 		dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n",
@@ -402,7 +405,7 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
 	case 100000000:
 		mpll_mul = 0x19;
 		if (ref_clk_sel < 2)
-			uctl_ctl.s.ref_clk_fsel = 0x27;
+			ref_clk_fsel = 0x27;
 		break;
 	case 50000000:
 		mpll_mul = 0x32;
@@ -411,28 +414,32 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
 		mpll_mul = 0x28;
 		break;
 	}
-	uctl_ctl.s.mpll_multiplier = mpll_mul;
+	val &= ~USBDRD_UCTL_CTL_REF_CLK_FSEL;
+	val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_FSEL, ref_clk_fsel);
+
+	val &= ~USBDRD_UCTL_CTL_MPLL_MULTIPLIER;
+	val |= FIELD_PREP(USBDRD_UCTL_CTL_MPLL_MULTIPLIER, mpll_mul);
 
 	/* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */
-	uctl_ctl.s.ssc_en = 1;
+	val |= USBDRD_UCTL_CTL_SSC_EN;
 
 	/* Step 5c: Enable SuperSpeed. */
-	uctl_ctl.s.ref_ssp_en = 1;
+	val |= USBDRD_UCTL_CTL_REF_SSP_EN;
 
 	/* Step 5d: Configure PHYs. SKIP */
 
 	/* Step 6a & 6b: Power up PHYs. */
-	uctl_ctl.s.hs_power_en = 1;
-	uctl_ctl.s.ss_power_en = 1;
-	cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
+	val |= USBDRD_UCTL_CTL_HS_POWER_EN;
+	val |= USBDRD_UCTL_CTL_SS_POWER_EN;
+	dwc3_octeon_writeq(uctl_ctl_reg, val);
 
 	/* Step 7: Wait 10 controller-clock cycles to take effect. */
 	udelay(10);
 
 	/* Step 8a: Deassert UCTL reset signal. */
-	uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
-	uctl_ctl.s.uctl_rst = 0;
-	cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
+	val = dwc3_octeon_readq(uctl_ctl_reg);
+	val &= ~USBDRD_UCTL_CTL_UCTL_RST;
+	dwc3_octeon_writeq(uctl_ctl_reg, val);
 
 	/* Step 8b: Wait 10 controller-clock cycles. */
 	udelay(10);
@@ -442,53 +449,49 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
 		return -EINVAL;
 
 	/* Step 8d: Deassert UAHC reset signal. */
-	uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
-	uctl_ctl.s.uahc_rst = 0;
-	cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
+	val = dwc3_octeon_readq(uctl_ctl_reg);
+	val &= ~USBDRD_UCTL_CTL_UAHC_RST;
+	dwc3_octeon_writeq(uctl_ctl_reg, val);
 
 	/* Step 8e: Wait 10 controller-clock cycles. */
 	udelay(10);
 
 	/* Step 9: Enable conditional coprocessor clock of UCTL. */
-	uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
-	uctl_ctl.s.csclk_en = 1;
-	cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
+	val = dwc3_octeon_readq(uctl_ctl_reg);
+	val |= USBDRD_UCTL_CTL_CSCLK_EN;
+	dwc3_octeon_writeq(uctl_ctl_reg, val);
 
 	/*Step 10: Set for host mode only. */
-	uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
-	uctl_ctl.s.drd_mode = 0;
-	cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
+	val = dwc3_octeon_readq(uctl_ctl_reg);
+	val &= ~USBDRD_UCTL_CTL_DRD_MODE;
+	dwc3_octeon_writeq(uctl_ctl_reg, val);
 
 	return 0;
 }
 
-static void __init dwc3_octeon_set_endian_mode(u64 base)
+static void __init dwc3_octeon_set_endian_mode(void __iomem *base)
 {
-#define UCTL_SHIM_CFG	0xe8
-	union cvm_usbdrd_uctl_shim_cfg shim_cfg;
+	u64 val;
+	void __iomem *uctl_shim_cfg_reg = base + USBDRD_UCTL_SHIM_CFG;
 
-	shim_cfg.u64 = cvmx_read_csr(base + UCTL_SHIM_CFG);
+	val = dwc3_octeon_readq(uctl_shim_cfg_reg);
+	val &= ~USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE;
+	val &= ~USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE;
 #ifdef __BIG_ENDIAN
-	shim_cfg.s.dma_endian_mode = 1;
-	shim_cfg.s.csr_endian_mode = 1;
-#else
-	shim_cfg.s.dma_endian_mode = 0;
-	shim_cfg.s.csr_endian_mode = 0;
+	val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE, 1);
+	val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE, 1);
 #endif
-	cvmx_write_csr(base + UCTL_SHIM_CFG, shim_cfg.u64);
+	dwc3_octeon_writeq(uctl_shim_cfg_reg, val);
 }
 
-#define CVMX_USBDRDX_UCTL_CTL(index)				\
-		(CVMX_ADD_IO_SEG(0x0001180068000000ull) +	\
-		((index & 1) * 0x1000000ull))
-static void __init dwc3_octeon_phy_reset(u64 base)
+static void __init dwc3_octeon_phy_reset(void __iomem *base)
 {
-	union cvm_usbdrd_uctl_ctl uctl_ctl;
-	int index = (base >> 24) & 1;
+	u64 val;
+	void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL;
 
-	uctl_ctl.u64 = cvmx_read_csr(CVMX_USBDRDX_UCTL_CTL(index));
-	uctl_ctl.s.uphy_rst = 0;
-	cvmx_write_csr(CVMX_USBDRDX_UCTL_CTL(index), uctl_ctl.u64);
+	val = dwc3_octeon_readq(uctl_ctl_reg);
+	val &= ~USBDRD_UCTL_CTL_UPHY_RST;
+	dwc3_octeon_writeq(uctl_ctl_reg, val);
 }
 
 static int __init dwc3_octeon_device_init(void)
@@ -527,10 +530,10 @@ static int __init dwc3_octeon_device_init(void)
 			}
 
 			mutex_lock(&dwc3_octeon_clocks_mutex);
-			if (dwc3_octeon_clocks_start(&pdev->dev, (u64)base) == 0)
+			if (dwc3_octeon_clocks_start(&pdev->dev, base) == 0)
 				dev_info(&pdev->dev, "clocks initialized.\n");
-			dwc3_octeon_set_endian_mode((u64)base);
-			dwc3_octeon_phy_reset((u64)base);
+			dwc3_octeon_set_endian_mode(base);
+			dwc3_octeon_phy_reset(base);
 			mutex_unlock(&dwc3_octeon_clocks_mutex);
 			devm_iounmap(&pdev->dev, base);
 			devm_release_mem_region(&pdev->dev, res->start,